[msan] Handle X86 SIMD bitshift intrinsics.
llvm-svn: 202712
This commit is contained in:
Evgeniy Stepanov
parent
d21e2d76fc
commit
77be532f71
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@ -1827,6 +1827,48 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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}
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}
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// Given a scalar or vector, extract lower 64 bits (or less), and return all
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// zeroes if it is zero, and all ones otherwise.
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Value *Lower64ShadowExtend(IRBuilder<> &IRB, Value *S, Type *T) {
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if (S->getType()->isVectorTy())
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S = CreateShadowCast(IRB, S, IRB.getInt64Ty(), /* Signed */ true);
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assert(S->getType()->getPrimitiveSizeInBits() <= 64);
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Value *S2 = IRB.CreateICmpNE(S, getCleanShadow(S));
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return CreateShadowCast(IRB, S2, T, /* Signed */ true);
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}
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Value *VariableShadowExtend(IRBuilder<> &IRB, Value *S) {
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Type *T = S->getType();
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assert(T->isVectorTy());
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Value *S2 = IRB.CreateICmpNE(S, getCleanShadow(S));
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return IRB.CreateSExt(S2, T);
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}
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// \brief Instrument vector shift instrinsic.
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//
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// This function instruments intrinsics like int_x86_avx2_psll_w.
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// Intrinsic shifts %In by %ShiftSize bits.
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// %ShiftSize may be a vector. In that case the lower 64 bits determine shift
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// size, and the rest is ignored. Behavior is defined even if shift size is
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// greater than register (or field) width.
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void handleVectorShiftIntrinsic(IntrinsicInst &I, bool Variable) {
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assert(I.getNumArgOperands() == 2);
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IRBuilder<> IRB(&I);
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// If any of the S2 bits are poisoned, the whole thing is poisoned.
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// Otherwise perform the same shift on S1.
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Value *S1 = getShadow(&I, 0);
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Value *S2 = getShadow(&I, 1);
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Value *S2Conv = Variable ? VariableShadowExtend(IRB, S2)
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: Lower64ShadowExtend(IRB, S2, getShadowTy(&I));
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Value *V1 = I.getOperand(0);
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Value *V2 = I.getOperand(1);
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Value *Shift = IRB.CreateCall2(I.getCalledValue(),
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IRB.CreateBitCast(S1, V1->getType()), V2);
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Shift = IRB.CreateBitCast(Shift, getShadowTy(&I));
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setShadow(&I, IRB.CreateOr(Shift, S2Conv));
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setOriginForNaryOp(I);
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}
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void visitIntrinsicInst(IntrinsicInst &I) {
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switch (I.getIntrinsicID()) {
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case llvm::Intrinsic::bswap:
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@ -1866,6 +1908,83 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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case llvm::Intrinsic::x86_sse_cvttps2pi:
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handleVectorConvertIntrinsic(I, 2);
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break;
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case llvm::Intrinsic::x86_avx512_psll_dq:
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case llvm::Intrinsic::x86_avx512_psrl_dq:
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case llvm::Intrinsic::x86_avx2_psll_w:
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case llvm::Intrinsic::x86_avx2_psll_d:
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case llvm::Intrinsic::x86_avx2_psll_q:
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case llvm::Intrinsic::x86_avx2_pslli_w:
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case llvm::Intrinsic::x86_avx2_pslli_d:
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case llvm::Intrinsic::x86_avx2_pslli_q:
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case llvm::Intrinsic::x86_avx2_psll_dq:
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case llvm::Intrinsic::x86_avx2_psrl_w:
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case llvm::Intrinsic::x86_avx2_psrl_d:
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case llvm::Intrinsic::x86_avx2_psrl_q:
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case llvm::Intrinsic::x86_avx2_psra_w:
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case llvm::Intrinsic::x86_avx2_psra_d:
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case llvm::Intrinsic::x86_avx2_psrli_w:
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case llvm::Intrinsic::x86_avx2_psrli_d:
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case llvm::Intrinsic::x86_avx2_psrli_q:
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case llvm::Intrinsic::x86_avx2_psrai_w:
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case llvm::Intrinsic::x86_avx2_psrai_d:
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case llvm::Intrinsic::x86_avx2_psrl_dq:
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case llvm::Intrinsic::x86_sse2_psll_w:
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case llvm::Intrinsic::x86_sse2_psll_d:
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case llvm::Intrinsic::x86_sse2_psll_q:
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case llvm::Intrinsic::x86_sse2_pslli_w:
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case llvm::Intrinsic::x86_sse2_pslli_d:
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case llvm::Intrinsic::x86_sse2_pslli_q:
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case llvm::Intrinsic::x86_sse2_psll_dq:
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case llvm::Intrinsic::x86_sse2_psrl_w:
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case llvm::Intrinsic::x86_sse2_psrl_d:
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case llvm::Intrinsic::x86_sse2_psrl_q:
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case llvm::Intrinsic::x86_sse2_psra_w:
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case llvm::Intrinsic::x86_sse2_psra_d:
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case llvm::Intrinsic::x86_sse2_psrli_w:
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case llvm::Intrinsic::x86_sse2_psrli_d:
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case llvm::Intrinsic::x86_sse2_psrli_q:
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case llvm::Intrinsic::x86_sse2_psrai_w:
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case llvm::Intrinsic::x86_sse2_psrai_d:
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case llvm::Intrinsic::x86_sse2_psrl_dq:
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case llvm::Intrinsic::x86_mmx_psll_w:
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case llvm::Intrinsic::x86_mmx_psll_d:
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case llvm::Intrinsic::x86_mmx_psll_q:
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case llvm::Intrinsic::x86_mmx_pslli_w:
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case llvm::Intrinsic::x86_mmx_pslli_d:
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case llvm::Intrinsic::x86_mmx_pslli_q:
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case llvm::Intrinsic::x86_mmx_psrl_w:
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case llvm::Intrinsic::x86_mmx_psrl_d:
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case llvm::Intrinsic::x86_mmx_psrl_q:
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case llvm::Intrinsic::x86_mmx_psra_w:
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case llvm::Intrinsic::x86_mmx_psra_d:
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case llvm::Intrinsic::x86_mmx_psrli_w:
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case llvm::Intrinsic::x86_mmx_psrli_d:
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case llvm::Intrinsic::x86_mmx_psrli_q:
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case llvm::Intrinsic::x86_mmx_psrai_w:
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case llvm::Intrinsic::x86_mmx_psrai_d:
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handleVectorShiftIntrinsic(I, /* Variable */ false);
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break;
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case llvm::Intrinsic::x86_avx2_psllv_d:
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case llvm::Intrinsic::x86_avx2_psllv_d_256:
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case llvm::Intrinsic::x86_avx2_psllv_q:
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case llvm::Intrinsic::x86_avx2_psllv_q_256:
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case llvm::Intrinsic::x86_avx2_psrlv_d:
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case llvm::Intrinsic::x86_avx2_psrlv_d_256:
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case llvm::Intrinsic::x86_avx2_psrlv_q:
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case llvm::Intrinsic::x86_avx2_psrlv_q_256:
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case llvm::Intrinsic::x86_avx2_psrav_d:
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case llvm::Intrinsic::x86_avx2_psrav_d_256:
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handleVectorShiftIntrinsic(I, /* Variable */ true);
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break;
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// Byte shifts are not implemented.
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// case llvm::Intrinsic::x86_avx512_psll_dq_bs:
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// case llvm::Intrinsic::x86_avx512_psrl_dq_bs:
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// case llvm::Intrinsic::x86_avx2_psll_dq_bs:
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// case llvm::Intrinsic::x86_avx2_psrl_dq_bs:
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// case llvm::Intrinsic::x86_sse2_psll_dq_bs:
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// case llvm::Intrinsic::x86_sse2_psrl_dq_bs:
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default:
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if (!handleUnknownIntrinsic(I))
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visitInstruction(I);
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@ -0,0 +1,100 @@
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; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
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; Test instrumentation of vector shift instructions.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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declare x86_mmx @llvm.x86.mmx.psll.d(x86_mmx, x86_mmx)
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declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>)
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declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>)
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declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
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declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32)
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declare <2 x i64> @llvm.x86.sse2.psll.dq.bs(<2 x i64>, i32)
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define i64 @test_mmx(i64 %x.coerce, i64 %y.coerce) {
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entry:
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%0 = bitcast i64 %x.coerce to <2 x i32>
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%1 = bitcast <2 x i32> %0 to x86_mmx
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%2 = bitcast i64 %y.coerce to x86_mmx
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%3 = tail call x86_mmx @llvm.x86.mmx.psll.d(x86_mmx %1, x86_mmx %2)
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%4 = bitcast x86_mmx %3 to <2 x i32>
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%5 = bitcast <2 x i32> %4 to <1 x i64>
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%6 = extractelement <1 x i64> %5, i32 0
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ret i64 %6
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}
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; CHECK: @test_mmx
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; CHECK: = icmp ne i64 {{.*}}, 0
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; CHECK: [[C:%.*]] = sext i1 {{.*}} to i64
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; CHECK: [[A:%.*]] = call x86_mmx @llvm.x86.mmx.psll.d(
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; CHECK: [[B:%.*]] = bitcast x86_mmx {{.*}}[[A]] to i64
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; CHECK: = or i64 {{.*}}[[B]], {{.*}}[[C]]
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; CHECK: call x86_mmx @llvm.x86.mmx.psll.d(
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; CHECK: ret i64
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define <8 x i16> @test_sse2_scalar(<8 x i16> %x, i32 %y) {
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entry:
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%0 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %x, i32 %y)
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ret <8 x i16> %0
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}
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; CHECK: @test_sse2_scalar
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; CHECK: = icmp ne i32 {{.*}}, 0
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; CHECK: = sext i1 {{.*}} to i128
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; CHECK: = bitcast i128 {{.*}} to <8 x i16>
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; CHECK: = call <8 x i16> @llvm.x86.sse2.pslli.w(
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; CHECK: = or <8 x i16>
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; CHECK: call <8 x i16> @llvm.x86.sse2.pslli.w(
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; CHECK: ret <8 x i16>
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define <8 x i16> @test_sse2(<8 x i16> %x, <8 x i16> %y) {
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entry:
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%0 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %x, <8 x i16> %y)
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ret <8 x i16> %0
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}
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; CHECK: @test_sse2
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; CHECK: = bitcast <8 x i16> {{.*}} to i128
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; CHECK: = trunc i128 {{.*}} to i64
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; CHECK: = icmp ne i64 {{.*}}, 0
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; CHECK: = sext i1 {{.*}} to i128
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; CHECK: = bitcast i128 {{.*}} to <8 x i16>
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; CHECK: = call <8 x i16> @llvm.x86.sse2.psrl.w(
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; CHECK: = or <8 x i16>
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; CHECK: call <8 x i16> @llvm.x86.sse2.psrl.w(
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; CHECK: ret <8 x i16>
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; Test variable shift (i.e. vector by vector).
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define <4 x i32> @test_avx2(<4 x i32> %x, <4 x i32> %y) {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %x, <4 x i32> %y)
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ret <4 x i32> %0
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}
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; CHECK: @test_avx2
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; CHECK: = icmp ne <4 x i32> {{.*}}, zeroinitializer
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; CHECK: = sext <4 x i1> {{.*}} to <4 x i32>
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; CHECK: = call <4 x i32> @llvm.x86.avx2.psllv.d(
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; CHECK: = or <4 x i32>
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; CHECK: = tail call <4 x i32> @llvm.x86.avx2.psllv.d(
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; CHECK: ret <4 x i32>
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define <8 x i32> @test_avx2_256(<8 x i32> %x, <8 x i32> %y) {
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entry:
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%0 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %x, <8 x i32> %y)
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ret <8 x i32> %0
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}
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; CHECK: @test_avx2_256
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; CHECK: = icmp ne <8 x i32> {{.*}}, zeroinitializer
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; CHECK: = sext <8 x i1> {{.*}} to <8 x i32>
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; CHECK: = call <8 x i32> @llvm.x86.avx2.psllv.d.256(
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; CHECK: = or <8 x i32>
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; CHECK: = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(
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; CHECK: ret <8 x i32>
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