I added several lines in X86 code generator that allow to choose
VSHUFPS/VSHUFPD instructions while lowering VECTOR_SHUFFLE node. I check a commuted VSHUFP mask. The patch was reviewed by Bruno. llvm-svn: 145099
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@ -3431,6 +3431,41 @@ static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
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return Mask;
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return Mask;
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}
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}
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/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
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/// the two vector operands have swapped position.
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static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
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unsigned NumElems = VT.getVectorNumElements();
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for (unsigned i = 0; i != NumElems; ++i) {
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int idx = Mask[i];
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if (idx < 0)
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continue;
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else if (idx < (int)NumElems)
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Mask[i] = idx + NumElems;
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else
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Mask[i] = idx - NumElems;
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}
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}
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/// isCommutedVSHUFP() - Return true if swapping operands will
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/// allow to use the "vshufpd" or "vshufps" instruction
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/// for 256-bit vectors
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static bool isCommutedVSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT,
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const X86Subtarget *Subtarget) {
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unsigned NumElems = VT.getVectorNumElements();
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if ((VT.getSizeInBits() != 256) || ((NumElems != 4) && (NumElems != 8)))
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return false;
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SmallVector<int, 8> CommutedMask;
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for (unsigned i = 0; i < NumElems; ++i)
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CommutedMask.push_back(Mask[i]);
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CommuteVectorShuffleMask(CommutedMask, VT);
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return (NumElems == 4) ? isVSHUFPDYMask(CommutedMask, VT, Subtarget):
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isVSHUFPSYMask(CommutedMask, VT, Subtarget);
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}
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a shuffle of elements that is suitable for input to 128-bit
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/// specifies a shuffle of elements that is suitable for input to 128-bit
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/// SHUFPS and SHUFPD.
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/// SHUFPS and SHUFPD.
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@ -4233,21 +4268,6 @@ static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
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SVOp->getOperand(0), &MaskVec[0]);
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SVOp->getOperand(0), &MaskVec[0]);
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}
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}
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/// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
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/// the two vector operands have swapped position.
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static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
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unsigned NumElems = VT.getVectorNumElements();
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for (unsigned i = 0; i != NumElems; ++i) {
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int idx = Mask[i];
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if (idx < 0)
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continue;
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else if (idx < (int)NumElems)
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Mask[i] = idx + NumElems;
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else
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Mask[i] = idx - NumElems;
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}
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}
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/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
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/// ShouldXformToMOVHLPS - Return true if the node should be transformed to
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/// match movhlps. The lower half elements should come from upper half of
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/// match movhlps. The lower half elements should come from upper half of
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/// V1 (and in order), and the upper half elements should come from the upper
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/// V1 (and in order), and the upper half elements should come from the upper
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@ -6986,6 +7006,17 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
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return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
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getShuffleVSHUFPDYImmediate(SVOp), DAG);
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getShuffleVSHUFPDYImmediate(SVOp), DAG);
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// Try to swap operands in the node to match x86 shuffle ops
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if (isCommutedVSHUFPMask(M, VT, Subtarget)) {
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// Now we need to commute operands.
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SVOp = cast<ShuffleVectorSDNode>(CommuteVectorShuffle(SVOp, DAG));
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V1 = SVOp->getOperand(0);
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V2 = SVOp->getOperand(1);
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unsigned Immediate = (NumElems == 4) ? getShuffleVSHUFPDYImmediate(SVOp):
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getShuffleVSHUFPSYImmediate(SVOp);
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return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, Immediate, DAG);
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}
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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// Since no target specific shuffle was selected for this generic one,
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// Since no target specific shuffle was selected for this generic one,
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// lower it into other known shuffles. FIXME: this isn't true yet, but
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// lower it into other known shuffles. FIXME: this isn't true yet, but
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@ -27,3 +27,17 @@ entry:
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 undef>
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 undef>
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ret <4 x double> %shuffle
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ret <4 x double> %shuffle
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}
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}
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; CHECK: vshufps $-55, %ymm
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define <8 x float> @E(<8 x float> %a, <8 x float> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 9, i32 10, i32 0, i32 3, i32 13, i32 14, i32 4, i32 7>
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ret <8 x float> %shuffle
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}
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; CHECK: vshufpd $8, %ymm
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define <4 x double> @F(<4 x double> %a, <4 x double> %b) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 7>
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ret <4 x double> %shuffle
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}
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