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[Hexagon] Clear kill flags from modified registers in peephole optimizer 

llvm-svn: 277727
This commit is contained in:
Krzysztof Parzyszek 2016-08-04 14:17:16 +00:00
parent f919d8b360
commit 7773c58458
2 changed files with 31 additions and 1 deletions
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5
llvm/lib/Target/Hexagon/HexagonPeephole.cpp
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@ -250,6 +250,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
// Change the 1st operand and, flip the opcode. // Change the 1st operand and, flip the opcode.
MI.getOperand(0).setReg(PeepholeSrc); MI.getOperand(0).setReg(PeepholeSrc);
MRI->clearKillFlags(PeepholeSrc);
int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode()); int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
MI.setDesc(QII->get(NewOp)); MI.setDesc(QII->get(NewOp));
Done = true; Done = true;
@ -280,6 +281,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
unsigned PSrc = MI.getOperand(PR).getReg(); unsigned PSrc = MI.getOperand(PR).getReg();
if (unsigned POrig = PeepholeMap.lookup(PSrc)) { if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
MI.getOperand(PR).setReg(POrig); MI.getOperand(PR).setReg(POrig);
MRI->clearKillFlags(POrig);
MI.setDesc(QII->get(NewOp)); MI.setDesc(QII->get(NewOp));
// Swap operands S1 and S2. // Swap operands S1 and S2.
MachineOperand Op1 = MI.getOperand(S1); MachineOperand Op1 = MI.getOperand(S1);
@ -304,6 +306,7 @@ void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
if (Src.isReg()) { if (Src.isReg()) {
Dst.setReg(Src.getReg()); Dst.setReg(Src.getReg());
Dst.setSubReg(Src.getSubReg()); Dst.setSubReg(Src.getSubReg());
MRI->clearKillFlags(Src.getReg());
} else if (Src.isImm()) { } else if (Src.isImm()) {
Dst.ChangeToImmediate(Src.getImm()); Dst.ChangeToImmediate(Src.getImm());
} else { } else {
@ -316,7 +319,7 @@ void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
Dst.setImm(Src.getImm()); Dst.setImm(Src.getImm());
} else if (Src.isReg()) { } else if (Src.isReg()) {
Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(), Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
Src.isKill(), Src.isDead(), Src.isUndef(), false, Src.isDead(), Src.isUndef(),
Src.isDebug()); Src.isDebug());
Dst.setSubReg(Src.getSubReg()); Dst.setSubReg(Src.getSubReg());
} else { } else {

27
llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll Normal file
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@ -0,0 +1,27 @@
; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
; CHECK: memw
; Check that the testcase compiles without errors.
target triple = "hexagon"
; Function Attrs: nounwind
define void @fred() #0 {
entry:
br label %for.cond
for.cond: ; preds = %entry
%0 = load i32, i32* undef, align 4
%mul = mul nsw i32 2, %0
%cmp = icmp slt i32 undef, %mul
br i1 %cmp, label %for.body, label %for.end13
for.body: ; preds = %for.cond
unreachable
for.end13: ; preds = %for.cond
ret void
}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }