Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:
we were storing into [FP+88] instead of [FP+92]. Improve codegen by emitting [FP+92], instead of emitting a copy of FP into another GPR which wouldn't be coallesced because FP isn't register allocated. llvm-svn: 24859
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@ -456,6 +456,8 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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if (RegValuesToPass.size() >= 6) {
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if (RegValuesToPass.size() >= 6) {
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ValToStore = Lo;
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ValToStore = Lo;
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ArgOffset += 4;
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ObjSize = 4;
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} else {
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} else {
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RegValuesToPass.push_back(Lo);
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RegValuesToPass.push_back(Lo);
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}
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}
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@ -464,7 +466,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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if (ValToStore.Val) {
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if (ValToStore.Val) {
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if (!StackPtr.Val) {
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if (!StackPtr.Val) {
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StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32);
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StackPtr = DAG.getRegister(V8::O6, MVT::i32);
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NullSV = DAG.getSrcValue(NULL);
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NullSV = DAG.getSrcValue(NULL);
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}
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}
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SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
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SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
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@ -893,6 +895,7 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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switch (N->getOpcode()) {
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switch (N->getOpcode()) {
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default: break;
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default: break;
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case ISD::Register: return Op;
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case ISD::FrameIndex: {
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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if (N->hasOneUse())
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if (N->hasOneUse())
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