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Rename "ADDO" to "SADDO" and "UADDO". The "UADDO" isn't equivalent to "ADDC" 

because the boolean it returns to indicate an overflow may not be treated like
as a flag. It could be stored to memory, for instance.

llvm-svn: 59780
This commit is contained in:
Bill Wendling 2008-11-21 02:12:42 +00:00
parent 74296c60ff
commit 77538cc510
4 changed files with 22 additions and 14 deletions
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15
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
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@ -250,13 +250,14 @@ namespace ISD {
// values. // values.
ADDE, SUBE, ADDE, SUBE,
// RESULT, OVERFLOW_FLAG, OUTCHAIN = ADDO(INCHAIN, LHS, RHS) - // RESULT, BOOL, OUTCHAIN = [SU]ADDO(INCHAIN, LHS, RHS) - Overflow-aware
// Overflow-aware node for arithmetic operations. This node takes two // node for arithmetic operations. This node takes two operands: the normal
// operands: the normal lhs and rhs to the add. It produces two results: the // lhs and rhs to the add. It produces two results: the normal result of the
// normal result of the add, and a flag indicating whether an overflow // add, and a boolean to indicate if an overflow occured (this isn't a flag,
// occured. This node is generated from the llvm.sadd.with.overflow // because it may be stored to memory, etc.). This node is generated from
// intrinsic. It is lowered by target-dependent code. // the llvm.sadd.with.overflow intrinsic. It is lowered by target-dependent
ADDO, // code.
SADDO, UADDO,
// Simple binary floating point operators. // Simple binary floating point operators.
FADD, FSUB, FMUL, FDIV, FREM, FADD, FSUB, FMUL, FDIV, FREM,

12
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -190,7 +190,8 @@ namespace {
SDValue visitBUILD_VECTOR(SDNode *N); SDValue visitBUILD_VECTOR(SDNode *N);
SDValue visitCONCAT_VECTORS(SDNode *N); SDValue visitCONCAT_VECTORS(SDNode *N);
SDValue visitVECTOR_SHUFFLE(SDNode *N); SDValue visitVECTOR_SHUFFLE(SDNode *N);
SDValue visitADDO(SDNode *N); SDValue visitSADDO(SDNode *N);
SDValue visitUADDO(SDNode *N);
SDValue XformToShuffleWithZero(SDNode *N); SDValue XformToShuffleWithZero(SDNode *N);
SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS);
@ -728,7 +729,8 @@ SDValue DAGCombiner::visit(SDNode *N) {
case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
case ISD::ADDO: return visitADDO(N); case ISD::SADDO: return visitSADDO(N);
case ISD::UADDO: return visitUADDO(N);
} }
return SDValue(); return SDValue();
} }
@ -5145,7 +5147,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
return SDValue(); return SDValue();
} }
SDValue DAGCombiner::visitADDO(SDNode *N) { SDValue DAGCombiner::visitSADDO(SDNode *N) {
SDValue Chain = N->getOperand(2); SDValue Chain = N->getOperand(2);
SDValue LHS = N->getOperand(0); SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1); SDValue RHS = N->getOperand(1);
@ -5173,6 +5175,10 @@ SDValue DAGCombiner::visitADDO(SDNode *N) {
return SDValue(N, 0); return SDValue(N, 0);
} }
SDValue DAGCombiner::visitUADDO(SDNode *N) {
return SDValue();
}
/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
/// an AND to a vector_shuffle with the destination vector and a zero vector. /// an AND to a vector_shuffle with the destination vector and a zero vector.
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>

3
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -5151,7 +5151,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::CARRY_FALSE: return "carry_false"; case ISD::CARRY_FALSE: return "carry_false";
case ISD::ADDC: return "addc"; case ISD::ADDC: return "addc";
case ISD::ADDE: return "adde"; case ISD::ADDE: return "adde";
case ISD::ADDO: return "addo"; case ISD::SADDO: return "saddo";
case ISD::UADDO: return "uaddo";
case ISD::SUBC: return "subc"; case ISD::SUBC: return "subc";
case ISD::SUBE: return "sube"; case ISD::SUBE: return "sube";
case ISD::SHL_PARTS: return "shl_parts"; case ISD::SHL_PARTS: return "shl_parts";

6
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -4094,7 +4094,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
} }
case Intrinsic::sadd_with_overflow: { case Intrinsic::sadd_with_overflow: {
// Convert to "ISD::ADDO" instruction. // Convert to "ISD::SADDO" instruction.
SDValue Chain = getRoot(); SDValue Chain = getRoot();
SDValue Op1 = getValue(I.getOperand(1)); SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2)); SDValue Op2 = getValue(I.getOperand(2));
@ -4103,7 +4103,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
MVT ValueVTs[] = { Ty, MVT::i1, MVT::Other }; MVT ValueVTs[] = { Ty, MVT::i1, MVT::Other };
SDValue Ops[] = { Op1, Op2, Chain }; SDValue Ops[] = { Op1, Op2, Chain };
SDValue Result = DAG.getNode(ISD::ADDO, DAG.getVTList(&ValueVTs[0], 3), SDValue Result = DAG.getNode(ISD::SADDO, DAG.getVTList(&ValueVTs[0], 3),
&Ops[0], 3); &Ops[0], 3);
setValue(&I, Result); setValue(&I, Result);
@ -4113,7 +4113,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
return 0; return 0;
} }
case Intrinsic::uadd_with_overflow: { case Intrinsic::uadd_with_overflow: {
// TODO: Convert to "ISD::ADDC" instruction. // TODO: Convert to "ISD::UADDO" instruction.
return 0; return 0;
} }