[RISCV] Add codegen for RV32F arithmetic and conversion operations
Currently, only a soft floating point ABI is supported. llvm-svn: 327976
This commit is contained in:
Alex Bradbury
parent
dca383123f
commit
76c29ee815
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@ -45,6 +45,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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// Set up the register classes.
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addRegisterClass(XLenVT, &RISCV::GPRRegClass);
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if (Subtarget.hasStdExtF())
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addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
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// Compute derived properties from the register classes.
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computeRegisterProperties(STI.getRegisterInfo());
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@ -103,6 +106,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::CTLZ, XLenVT, Expand);
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setOperationAction(ISD::CTPOP, XLenVT, Expand);
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if (Subtarget.hasStdExtF()) {
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setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
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}
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setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
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setOperationAction(ISD::BlockAddress, XLenVT, Custom);
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@ -491,7 +499,10 @@ static bool CC_RISCV(const DataLayout &DL, unsigned ValNo, MVT ValVT, MVT LocVT,
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unsigned XLen = DL.getLargestLegalIntTypeSizeInBits();
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assert(XLen == 32 || XLen == 64);
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MVT XLenVT = XLen == 32 ? MVT::i32 : MVT::i64;
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assert(ValVT == XLenVT && "Unexpected ValVT");
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if (ValVT == MVT::f32) {
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LocVT = MVT::i32;
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LocInfo = CCValAssign::BCvt;
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}
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assert(LocVT == XLenVT && "Unexpected LocVT");
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// Any return value split in to more than two values can't be returned
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@ -634,6 +645,7 @@ static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain,
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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EVT LocVT = VA.getLocVT();
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EVT ValVT = VA.getValVT();
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SDValue Val;
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unsigned VReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
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@ -645,8 +657,12 @@ static SDValue unpackFromRegLoc(SelectionDAG &DAG, SDValue Chain,
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llvm_unreachable("Unexpected CCValAssign::LocInfo");
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case CCValAssign::Full:
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case CCValAssign::Indirect:
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return Val;
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break;
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case CCValAssign::BCvt:
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Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
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break;
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}
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return Val;
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}
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// The caller is responsible for loading the full value if the argument is
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@ -867,6 +883,9 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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switch (VA.getLocInfo()) {
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case CCValAssign::Full:
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break;
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case CCValAssign::BCvt:
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ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), ArgValue);
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break;
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case CCValAssign::Indirect: {
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// Store the argument in a stack slot and pass its address.
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SDValue SpillSlot = DAG.CreateStackTemporary(Outs[i].ArgVT);
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@ -981,7 +1000,16 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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Chain = RetValue.getValue(1);
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Glue = RetValue.getValue(2);
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assert(VA.getLocInfo() == CCValAssign::Full && "Unknown loc info!");
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unknown loc info!");
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case CCValAssign::Full:
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break;
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case CCValAssign::BCvt:
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RetValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), RetValue);
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break;
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}
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InVals.push_back(RetValue);
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}
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@ -1003,6 +1031,22 @@ bool RISCVTargetLowering::CanLowerReturn(
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return true;
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}
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static SDValue packIntoRegLoc(SelectionDAG &DAG, SDValue Val,
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const CCValAssign &VA, const SDLoc &DL) {
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EVT LocVT = VA.getLocVT();
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unexpected CCValAssign::LocInfo");
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case CCValAssign::Full:
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break;
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case CCValAssign::BCvt:
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Val = DAG.getNode(ISD::BITCAST, DL, LocVT, Val);
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break;
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}
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return Val;
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}
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SDValue
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RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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@ -1027,8 +1071,7 @@ RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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SDValue Val = OutVals[i];
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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assert(VA.getLocInfo() == CCValAssign::Full &&
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"Unexpected CCValAssign::LocInfo");
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Val = packIntoRegLoc(DAG, Val, VA, DL);
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Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
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@ -220,3 +220,59 @@ def : InstAlias<"fsflags $rs", (CSRRW X0, 0x001, GPR:$rs), 2>;
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def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, 0x001, uimm5:$imm)>;
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def : InstAlias<"fsflagsi $imm", (CSRRWI X0, 0x001, uimm5:$imm), 2>;
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} // Predicates = [HasStdExtF]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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/// Generic pattern classes
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class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>
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: Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>;
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class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
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: Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>;
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let Predicates = [HasStdExtF] in {
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/// Float conversion operations
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// Moves (no conversion)
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def : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>;
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def : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>;
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// FP->[u]int. Round-to-zero must be used
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def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
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def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
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// [u]int->fp. Match GCC and default to using dynamic rounding mode.
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def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
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def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
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/// Float arithmetic operations
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def : PatFpr32Fpr32DynFrm<fadd, FADD_S>;
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def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
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def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
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def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
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def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
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def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
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def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
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def : PatFpr32Fpr32<fcopysign, FSGNJ_S>;
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def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
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// The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
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// canonical NaN when given a signaling NaN. This doesn't match the LLVM
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// behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
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// draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
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// matches LLVM's fminnum and fmaxnum
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// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
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def : PatFpr32Fpr32<fminnum, FMIN_S>;
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def : PatFpr32Fpr32<fmaxnum, FMAX_S>;
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def : PatFpr32Fpr32<setoeq, FEQ_S>;
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def : PatFpr32Fpr32<setolt, FLT_S>;
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def : PatFpr32Fpr32<setole, FLE_S>;
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} // Predicates = [HasStdExtF]
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@ -0,0 +1,190 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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define float @fadd_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fadd_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = fadd float %a, %b
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ret float %1
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}
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define float @fsub_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fsub_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fsub.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = fsub float %a, %b
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ret float %1
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}
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define float @fmul_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fmul_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fmul.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = fmul float %a, %b
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ret float %1
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}
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define float @fdiv_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fdiv_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fdiv.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = fdiv float %a, %b
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ret float %1
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}
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declare float @llvm.sqrt.f32(float)
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define float @fsqrt_s(float %a) nounwind {
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; RV32IF-LABEL: fsqrt_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fsqrt.s ft0, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = call float @llvm.sqrt.f32(float %a)
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ret float %1
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}
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declare float @llvm.copysign.f32(float, float)
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define float @fsgnj_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fsgnj_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = call float @llvm.copysign.f32(float %a, float %b)
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ret float %1
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}
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define float @fneg_s(float %a) nounwind {
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; TODO: doesn't test the fneg selection pattern because
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; DAGCombiner::visitBITCAST will generate a xor on the incoming integer
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; argument
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; RV32IF-LABEL: fneg_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a1, 524288
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; RV32IF-NEXT: mv a1, a1
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; RV32IF-NEXT: xor a0, a0, a1
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; RV32IF-NEXT: ret
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%1 = fsub float -0.0, %a
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ret float %1
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}
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define float @fsgnjn_s(float %a, float %b) nounwind {
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; TODO: fsgnjn.s isn't selected because DAGCombiner::visitBITCAST will convert
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; (bitconvert (fneg x)) to a xor
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; RV32IF-LABEL: fsgnjn_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a2, 524288
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; RV32IF-NEXT: mv a2, a2
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; RV32IF-NEXT: xor a1, a1, a2
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fsgnj.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = fsub float -0.0, %b
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%2 = call float @llvm.copysign.f32(float %a, float %1)
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ret float %2
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}
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declare float @llvm.fabs.f32(float)
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define float @fabs_s(float %a) nounwind {
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; TODO: doesn't test the fabs selection pattern because
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; DAGCombiner::visitBITCAST will generate an and on the incoming integer
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; argument
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; RV32IF-LABEL: fabs_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: lui a1, 524288
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; RV32IF-NEXT: addi a1, a1, -1
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; RV32IF-NEXT: and a0, a0, a1
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; RV32IF-NEXT: ret
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%1 = call float @llvm.fabs.f32(float %a)
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ret float %1
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}
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declare float @llvm.minnum.f32(float, float)
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define float @fmin_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fmin_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fmin.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = call float @llvm.minnum.f32(float %a, float %b)
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ret float %1
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}
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declare float @llvm.maxnum.f32(float, float)
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define float @fmax_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fmax_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fmax.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = call float @llvm.maxnum.f32(float %a, float %b)
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ret float %1
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}
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define i32 @feq_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: feq_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: feq.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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%1 = fcmp oeq float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @flt_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: flt_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: flt.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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%1 = fcmp olt float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fle_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: fle_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fle.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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%1 = fcmp ole float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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@ -0,0 +1,72 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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define i32 @fcvt_w_s(float %a) nounwind {
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; RV32IF-LABEL: fcvt_w_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
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; RV32IF-NEXT: ret
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%1 = fptosi float %a to i32
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ret i32 %1
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}
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define i32 @fcvt_wu_s(float %a) nounwind {
|
||||
; RV32IF-LABEL: fcvt_wu_s:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: fmv.w.x ft0, a0
|
||||
; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz
|
||||
; RV32IF-NEXT: ret
|
||||
%1 = fptoui float %a to i32
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @fmv_x_w(float %a, float %b) nounwind {
|
||||
; RV32IF-LABEL: fmv_x_w:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: fmv.w.x ft0, a1
|
||||
; RV32IF-NEXT: fmv.w.x ft1, a0
|
||||
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
|
||||
; RV32IF-NEXT: fmv.x.w a0, ft0
|
||||
; RV32IF-NEXT: ret
|
||||
; Ensure fmv.x.w is generated even for a soft float calling convention
|
||||
%1 = fadd float %a, %b
|
||||
%2 = bitcast float %1 to i32
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define float @fcvt_s_w(i32 %a) nounwind {
|
||||
; RV32IF-LABEL: fcvt_s_w:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: fcvt.s.w ft0, a0
|
||||
; RV32IF-NEXT: fmv.x.w a0, ft0
|
||||
; RV32IF-NEXT: ret
|
||||
%1 = sitofp i32 %a to float
|
||||
ret float %1
|
||||
}
|
||||
|
||||
define float @fcvt_s_wu(i32 %a) nounwind {
|
||||
; RV32IF-LABEL: fcvt_s_wu:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: fcvt.s.wu ft0, a0
|
||||
; RV32IF-NEXT: fmv.x.w a0, ft0
|
||||
; RV32IF-NEXT: ret
|
||||
%1 = uitofp i32 %a to float
|
||||
ret float %1
|
||||
}
|
||||
|
||||
define float @fmv_w_x(i32 %a, i32 %b) nounwind {
|
||||
; RV32IF-LABEL: fmv_w_x:
|
||||
; RV32IF: # %bb.0:
|
||||
; RV32IF-NEXT: fmv.w.x ft0, a1
|
||||
; RV32IF-NEXT: fmv.w.x ft1, a0
|
||||
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
|
||||
; RV32IF-NEXT: fmv.x.w a0, ft0
|
||||
; RV32IF-NEXT: ret
|
||||
; Ensure fmv.w.x is generated even for a soft float calling convention
|
||||
%1 = bitcast i32 %a to float
|
||||
%2 = bitcast i32 %b to float
|
||||
%3 = fadd float %1, %2
|
||||
ret float %3
|
||||
}
|
||||
Loading…
Reference in New Issue