[AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+scalar) store instructions.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46680 llvm-svn: 332584
This commit is contained in:
Sander de Smalen
parent
2ca16899ec
commit
75cfa34156
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@ -342,7 +342,7 @@ let Predicates = [HasSVE] in {
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defm SST1W_D_SCALED : sve_mem_sst_sv_64_scaled<0b10, "st1w", ZPR64ExtLSL32>;
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defm SST1D_SCALED : sve_mem_sst_sv_64_scaled<0b11, "st1d", ZPR64ExtLSL64>;
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// ST{2,3,4}{B,H,W,D} with immediate
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// ST(2|3|4) structured stores (register + immediate)
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defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b, "st2b", simm4s2>;
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defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b, "st3b", simm4s3>;
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defm ST4B_IMM : sve_mem_est_si<0b00, 0b11, ZZZZ_b, "st4b", simm4s4>;
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@ -356,6 +356,20 @@ let Predicates = [HasSVE] in {
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defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4s3>;
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defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>;
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// ST(2|3|4) structured stores (register + register)
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def ST2B : sve_mem_est_ss<0b00, 0b01, ZZ_b, "st2b", GPR64NoXZRshifted8>;
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def ST3B : sve_mem_est_ss<0b00, 0b10, ZZZ_b, "st3b", GPR64NoXZRshifted8>;
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def ST4B : sve_mem_est_ss<0b00, 0b11, ZZZZ_b, "st4b", GPR64NoXZRshifted8>;
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def ST2H : sve_mem_est_ss<0b01, 0b01, ZZ_h, "st2h", GPR64NoXZRshifted16>;
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def ST3H : sve_mem_est_ss<0b01, 0b10, ZZZ_h, "st3h", GPR64NoXZRshifted16>;
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def ST4H : sve_mem_est_ss<0b01, 0b11, ZZZZ_h, "st4h", GPR64NoXZRshifted16>;
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def ST2W : sve_mem_est_ss<0b10, 0b01, ZZ_s, "st2w", GPR64NoXZRshifted32>;
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def ST3W : sve_mem_est_ss<0b10, 0b10, ZZZ_s, "st3w", GPR64NoXZRshifted32>;
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def ST4W : sve_mem_est_ss<0b10, 0b11, ZZZZ_s, "st4w", GPR64NoXZRshifted32>;
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def ST2D : sve_mem_est_ss<0b11, 0b01, ZZ_d, "st2d", GPR64NoXZRshifted64>;
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def ST3D : sve_mem_est_ss<0b11, 0b10, ZZZ_d, "st3d", GPR64NoXZRshifted64>;
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def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>;
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// Non-temporal contiguous stores (register + immediate)
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defm STNT1B_ZRI : sve_mem_cstnt_si<0b00, "stnt1b", Z_b, ZPR8>;
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defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>;
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@ -574,6 +574,28 @@ multiclass sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
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(!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
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}
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class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
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string asm, RegisterOperand gprty>
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: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
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asm, "\t$Zt, $Pg, [$Rn, $Rm]",
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"",
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[]>, Sched<[]> {
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bits<3> Pg;
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bits<5> Rm;
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bits<5> Rn;
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bits<5> Zt;
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let Inst{31-25} = 0b1110010;
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let Inst{24-23} = sz;
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let Inst{22-21} = nregs;
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let Inst{20-16} = Rm;
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let Inst{15-13} = 0b011;
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let Inst{12-10} = Pg;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Zt;
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let mayStore = 1;
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}
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class sve_mem_cst_ss_base<bits<4> dtype, string asm,
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RegisterOperand listty, RegisterOperand gprty>
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: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
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@ -29,6 +29,30 @@ st2b {z7.b, z8.b}, p3, [x1, #5, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st2b { z0.b, z1.b }, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
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// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2b { z0.b, z1.b }, p0, [x0, x0, lsl #1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
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// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x0, lsl #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2b { z0.b, z1.b }, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
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// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2b { z0.b, z1.b }, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
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// CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// error: restricted predicate has range [0, 7].
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@ -7,6 +7,18 @@
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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st2b { z0.b, z1.b }, p0, [x0, x0]
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// CHECK-INST: st2b { z0.b, z1.b }, p0, [x0, x0]
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// CHECK-ENCODING: [0x00,0x60,0x20,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 20 e4 <unknown>
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st2b { z5.b, z6.b }, p3, [x17, x16]
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// CHECK-INST: st2b { z5.b, z6.b }, p3, [x17, x16]
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// CHECK-ENCODING: [0x25,0x6e,0x30,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 25 6e 30 e4 <unknown>
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st2b { z0.b, z1.b }, p0, [x0]
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// CHECK-INST: st2b { z0.b, z1.b }, p0, [x0]
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// CHECK-ENCODING: [0x00,0xe0,0x30,0xe4]
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@ -29,6 +29,35 @@ st2d {z7.d, z8.d}, p3, [x1, #5, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st2d { z0.d, z1.d }, p0, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2d { z0.d, z1.d }, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2d { z0.d, z1.d }, p0, [x0, x0, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2d { z0.d, z1.d }, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2d { z0.d, z1.d }, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
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// CHECK-NEXT: st2d { z0.d, z1.d }, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// error: restricted predicate has range [0, 7].
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@ -7,6 +7,18 @@
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]
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// CHECK-INST: st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]
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// CHECK-ENCODING: [0x00,0x60,0xa0,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 a0 e5 <unknown>
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st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]
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// CHECK-INST: st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]
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// CHECK-ENCODING: [0x25,0x6e,0xb0,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 25 6e b0 e5 <unknown>
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st2d { z0.d, z1.d }, p0, [x0]
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// CHECK-INST: st2d { z0.d, z1.d }, p0, [x0]
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// CHECK-ENCODING: [0x00,0xe0,0xb0,0xe5]
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@ -29,6 +29,35 @@ st2h {z7.h, z8.h}, p3, [x1, #5, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st2h { z0.h, z1.h }, p0, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2h { z0.h, z1.h }, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2h { z0.h, z1.h }, p0, [x0, x0, lsl #2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, x0, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2h { z0.h, z1.h }, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2h { z0.h, z1.h }, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
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// CHECK-NEXT: st2h { z0.h, z1.h }, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// error: restricted predicate has range [0, 7].
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@ -7,6 +7,18 @@
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]
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// CHECK-INST: st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]
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// CHECK-ENCODING: [0x00,0x60,0xa0,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 a0 e4 <unknown>
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st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]
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// CHECK-INST: st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]
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// CHECK-ENCODING: [0x25,0x6e,0xb0,0xe4]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 25 6e b0 e4 <unknown>
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st2h { z0.h, z1.h }, p0, [x0]
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// CHECK-INST: st2h { z0.h, z1.h }, p0, [x0]
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// CHECK-ENCODING: [0x00,0xe0,0xb0,0xe4]
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@ -29,6 +29,35 @@ st2w {z7.s, z8.s}, p3, [x1, #5, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st2w { z0.s, z1.s }, p0, [x0, x0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, x0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2w { z0.s, z1.s }, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, xzr]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2w { z0.s, z1.s }, p0, [x0, x0, lsl #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, x0, lsl #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2w { z0.s, z1.s }, p0, [x0, w0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, w0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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st2w { z0.s, z1.s }, p0, [x0, w0, uxtw]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
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// CHECK-NEXT: st2w { z0.s, z1.s }, p0, [x0, w0, uxtw]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// error: restricted predicate has range [0, 7].
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@ -7,6 +7,18 @@
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]
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// CHECK-INST: st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]
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// CHECK-ENCODING: [0x00,0x60,0x20,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 00 60 20 e5 <unknown>
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st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]
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// CHECK-INST: st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]
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// CHECK-ENCODING: [0x25,0x6e,0x30,0xe5]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 25 6e 30 e5 <unknown>
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st2w { z0.s, z1.s }, p0, [x0]
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// CHECK-INST: st2w { z0.s, z1.s }, p0, [x0]
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// CHECK-ENCODING: [0x00,0xe0,0x30,0xe5]
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@ -29,6 +29,30 @@ st3b {z7.b, z8.b, z9.b}, p3, [x1, #5, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
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st3b { z0.b, z1.b, z2.b }, p0, [x0, xzr]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
|
||||
// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, xzr]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3b { z0.b, z1.b, z2.b }, p0, [x0, x0, lsl #1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
|
||||
// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x0, lsl #1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3b { z0.b, z1.b, z2.b }, p0, [x0, w0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
|
||||
// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, w0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3b { z0.b, z1.b, z2.b }, p0, [x0, w0, uxtw]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
|
||||
// CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, w0, uxtw]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// error: restricted predicate has range [0, 7].
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,18 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
st3b { z0.b, z1.b, z2.b }, p0, [x0, x0]
|
||||
// CHECK-INST: st3b { z0.b, z1.b, z2.b }, p0, [x0, x0]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x40,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 40 e4 <unknown>
|
||||
|
||||
st3b { z5.b, z6.b, z7.b }, p3, [x17, x16]
|
||||
// CHECK-INST: st3b { z5.b, z6.b, z7.b }, p3, [x17, x16]
|
||||
// CHECK-ENCODING: [0x25,0x6e,0x50,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 25 6e 50 e4 <unknown>
|
||||
|
||||
st3b { z0.b, z1.b, z2.b }, p0, [x0]
|
||||
// CHECK-INST: st3b { z0.b, z1.b, z2.b }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x50,0xe4]
|
||||
|
|
|
|||
|
|
@ -29,6 +29,35 @@ st3d {z7.d, z8.d, z9.d}, p3, [x1, #5, MUL VL]
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + scalar addressing modes
|
||||
|
||||
st3d { z0.d, z1.d, z2.d }, p0, [x0, x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3d { z0.d, z1.d, z2.d }, p0, [x0, xzr]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, xzr]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3d { z0.d, z1.d, z2.d }, p0, [x0, w0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, w0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st3d { z0.d, z1.d, z2.d }, p0, [x0, w0, uxtw]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// error: restricted predicate has range [0, 7].
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,18 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
|
||||
// CHECK-INST: st3d { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
|
||||
// CHECK-ENCODING: [0x00,0x60,0xc0,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 c0 e5 <unknown>
|
||||
|
||||
st3d { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
|
||||
// CHECK-INST: st3d { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
|
||||
// CHECK-ENCODING: [0x25,0x6e,0xd0,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 25 6e d0 e5 <unknown>
|
||||
|
||||
st3d { z0.d, z1.d, z2.d }, p0, [x0]
|
||||
// CHECK-INST: st3d { z0.d, z1.d, z2.d }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0xd0,0xe5]
|
||||
|
|
|
|||
|
|
@ -29,6 +29,35 @@ st3h {z7.h, z8.h, z9.h}, p3, [x1, #5, MUL VL]
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + scalar addressing modes
|
||||
|
||||
st3h { z0.h, z1.h, z2.h }, p0, [x0, x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3h { z0.h, z1.h, z2.h }, p0, [x0, xzr]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, xzr]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3h { z0.h, z1.h, z2.h }, p0, [x0, w0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, w0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3h { z0.h, z1.h, z2.h }, p0, [x0, w0, uxtw]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st3h { z0.h, z1.h, z2.h }, p0, [x0, w0, uxtw]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// error: restricted predicate has range [0, 7].
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,18 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
|
||||
// CHECK-INST: st3h { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
|
||||
// CHECK-ENCODING: [0x00,0x60,0xc0,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 c0 e4 <unknown>
|
||||
|
||||
st3h { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
|
||||
// CHECK-INST: st3h { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
|
||||
// CHECK-ENCODING: [0x25,0x6e,0xd0,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 25 6e d0 e4 <unknown>
|
||||
|
||||
st3h { z0.h, z1.h, z2.h }, p0, [x0]
|
||||
// CHECK-INST: st3h { z0.h, z1.h, z2.h }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0xd0,0xe4]
|
||||
|
|
|
|||
|
|
@ -29,6 +29,35 @@ st3w {z7.s, z8.s, z9.s}, p3, [x1, #5, MUL VL]
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + scalar addressing modes
|
||||
|
||||
st3w { z0.s, z1.s, z2.s }, p0, [x0, x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3w { z0.s, z1.s, z2.s }, p0, [x0, xzr]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, xzr]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3w { z0.s, z1.s, z2.s }, p0, [x0, w0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, w0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st3w { z0.s, z1.s, z2.s }, p0, [x0, w0, uxtw]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// error: restricted predicate has range [0, 7].
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,18 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-INST: st3w { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x40,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 40 e5 <unknown>
|
||||
|
||||
st3w { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
|
||||
// CHECK-INST: st3w { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
|
||||
// CHECK-ENCODING: [0x25,0x6e,0x50,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 25 6e 50 e5 <unknown>
|
||||
|
||||
st3w { z0.s, z1.s, z2.s }, p0, [x0]
|
||||
// CHECK-INST: st3w { z0.s, z1.s, z2.s }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x50,0xe5]
|
||||
|
|
|
|||
|
|
@ -29,6 +29,30 @@ st4b {z7.b, z8.b, z9.b, z10.b}, p3, [x1, #5, MUL VL]
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + scalar addressing modes
|
||||
|
||||
st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, xzr]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
|
||||
// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, xzr]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0, lsl #1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
|
||||
// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0, lsl #1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
|
||||
// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
|
||||
// CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, w0, uxtw]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// error: restricted predicate has range [0, 7].
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,18 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
|
||||
// CHECK-INST: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x60,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 60 e4 <unknown>
|
||||
|
||||
st4b { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
|
||||
// CHECK-INST: st4b { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
|
||||
// CHECK-ENCODING: [0x25,0x6e,0x70,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 25 6e 70 e4 <unknown>
|
||||
|
||||
st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
|
||||
// CHECK-INST: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x70,0xe4]
|
||||
|
|
|
|||
|
|
@ -29,6 +29,36 @@ st4d {z7.d, z8.d, z9.d, z10.d}, p3, [x1, #5, MUL VL]
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + scalar addressing modes
|
||||
|
||||
st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, xzr]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, xzr]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0, uxtw]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
|
||||
// CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, w0, uxtw]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// error: restricted predicate has range [0, 7].
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,18 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
|
||||
// CHECK-INST: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
|
||||
// CHECK-ENCODING: [0x00,0x60,0xe0,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 e0 e5 <unknown>
|
||||
|
||||
st4d { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
|
||||
// CHECK-INST: st4d { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
|
||||
// CHECK-ENCODING: [0x25,0x6e,0xf0,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 25 6e f0 e5 <unknown>
|
||||
|
||||
st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
|
||||
// CHECK-INST: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0xf0,0xe5]
|
||||
|
|
|
|||
|
|
@ -29,6 +29,35 @@ st4h {z7.h, z8.h, z9.h, z10.h}, p3, [x1, #5, MUL VL]
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + scalar addressing modes
|
||||
|
||||
st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, xzr]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, xzr]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #2]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
||||
// CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, w0, uxtw]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// error: restricted predicate has range [0, 7].
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,18 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
|
||||
// CHECK-INST: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
|
||||
// CHECK-ENCODING: [0x00,0x60,0xe0,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 e0 e4 <unknown>
|
||||
|
||||
st4h { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
|
||||
// CHECK-INST: st4h { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
|
||||
// CHECK-ENCODING: [0x25,0x6e,0xf0,0xe4]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 25 6e f0 e4 <unknown>
|
||||
|
||||
st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
|
||||
// CHECK-INST: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0xf0,0xe4]
|
||||
|
|
|
|||
|
|
@ -29,6 +29,35 @@ st4w {z7.s, z8.s, z9.s, z10.s}, p3, [x1, #5, MUL VL]
|
|||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Invalid scalar + scalar addressing modes
|
||||
|
||||
st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, xzr]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, xzr]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #3]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #3]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
|
||||
// CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, w0, uxtw]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// error: restricted predicate has range [0, 7].
|
||||
|
||||
|
|
|
|||
|
|
@ -7,6 +7,18 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-INST: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
|
||||
// CHECK-ENCODING: [0x00,0x60,0x60,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 00 60 60 e5 <unknown>
|
||||
|
||||
st4w { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
|
||||
// CHECK-INST: st4w { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
|
||||
// CHECK-ENCODING: [0x25,0x6e,0x70,0xe5]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 25 6e 70 e5 <unknown>
|
||||
|
||||
st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
|
||||
// CHECK-INST: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
|
||||
// CHECK-ENCODING: [0x00,0xe0,0x70,0xe5]
|
||||
|
|
|
|||
Loading…
Reference in New Issue