Fix verification of explicit operands.
The machine code verifier did not check for explicit operands correctly. It used MachineInstr::getNumExplicitOperands, but that method may cheat and use the declared count in the TargetInstrDesc. Now we check the explicit operands one at a time in visitMachineOperand. llvm-svn: 82652
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@ -466,18 +466,11 @@ void
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MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
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MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
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{
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{
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const TargetInstrDesc &TI = MI->getDesc();
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const TargetInstrDesc &TI = MI->getDesc();
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if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
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if (MI->getNumOperands() < TI.getNumOperands()) {
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report("Too few operands", MI);
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report("Too few operands", MI);
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*OS << TI.getNumOperands() << " operands expected, but "
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*OS << TI.getNumOperands() << " operands expected, but "
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<< MI->getNumExplicitOperands() << " given.\n";
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<< MI->getNumExplicitOperands() << " given.\n";
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}
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}
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if (!TI.isVariadic()) {
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if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
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report("Too many operands", MI);
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*OS << TI.getNumOperands() << " operands expected, but "
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<< MI->getNumExplicitOperands() << " given.\n";
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}
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}
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}
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}
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void
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void
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@ -494,6 +487,16 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
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report("Explicit definition marked as use", MO, MONum);
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report("Explicit definition marked as use", MO, MONum);
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else if (MO->isImplicit())
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else if (MO->isImplicit())
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report("Explicit definition marked as implicit", MO, MONum);
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report("Explicit definition marked as implicit", MO, MONum);
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} else if (MONum < TI.getNumOperands()) {
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if (MO->isReg()) {
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if (MO->isDef())
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report("Explicit operand marked as def", MO, MONum);
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if (MO->isImplicit())
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report("Explicit operand marked as implicit", MO, MONum);
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}
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} else {
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if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic())
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report("Extra explicit operand on non-variadic instruction", MO, MONum);
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}
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}
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switch (MO->getType()) {
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switch (MO->getType()) {
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