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Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) 

and register spills.

llvm-svn: 83435
This commit is contained in:
Anton Korobeynikov 2009-10-07 00:06:35 +00:00
parent 6ba26317ce
commit 75b59fb055
2 changed files with 34 additions and 12 deletions
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34
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -21,6 +21,8 @@
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCAsmInfo.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
@ -665,27 +667,35 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
MachineMemOperand *MMO =
MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
MachineMemOperand::MOStore, 0,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
if (RC == ARM::GPRRegisterClass) { if (RC == ARM::GPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addReg(0).addImm(0)); .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
} else if (RC == ARM::DPRRegisterClass || } else if (RC == ARM::DPRRegisterClass ||
RC == ARM::DPR_VFP2RegisterClass || RC == ARM::DPR_VFP2RegisterClass ||
RC == ARM::DPR_8RegisterClass) { RC == ARM::DPR_8RegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
} else if (RC == ARM::SPRRegisterClass) { } else if (RC == ARM::SPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
.addReg(SrcReg, getKillRegState(isKill)) .addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
} else { } else {
assert((RC == ARM::QPRRegisterClass || assert((RC == ARM::QPRRegisterClass ||
RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
// FIXME: Neon instructions should support predicates // FIXME: Neon instructions should support predicates
BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill)) BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0); .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} }
} }
@ -695,23 +705,31 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
DebugLoc DL = DebugLoc::getUnknownLoc(); DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
MachineMemOperand *MMO =
MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
MachineMemOperand::MOLoad, 0,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
if (RC == ARM::GPRRegisterClass) { if (RC == ARM::GPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
.addFrameIndex(FI).addReg(0).addImm(0)); .addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO));
} else if (RC == ARM::DPRRegisterClass || } else if (RC == ARM::DPRRegisterClass ||
RC == ARM::DPR_VFP2RegisterClass || RC == ARM::DPR_VFP2RegisterClass ||
RC == ARM::DPR_8RegisterClass) { RC == ARM::DPR_8RegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
.addFrameIndex(FI).addImm(0)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
} else if (RC == ARM::SPRRegisterClass) { } else if (RC == ARM::SPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
.addFrameIndex(FI).addImm(0)); .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
} else { } else {
assert((RC == ARM::QPRRegisterClass || assert((RC == ARM::QPRRegisterClass ||
RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!"); RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
// FIXME: Neon instructions should support predicates // FIXME: Neon instructions should support predicates
BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0); BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} }
} }

12
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1303,17 +1303,20 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
CPAddr, NULL, 0); CPAddr,
PseudoSourceValue::getConstantPool(), 0);
SDValue Chain = Result.getValue(1); SDValue Chain = Result.getValue(1);
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
if (!UseGOTOFF) if (!UseGOTOFF)
Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); Result = DAG.getLoad(PtrVT, dl, Chain, Result,
PseudoSourceValue::getGOT(), 0);
return Result; return Result;
} else { } else {
SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
PseudoSourceValue::getConstantPool(), 0);
} }
} }
@ -1360,7 +1363,8 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
ARMPCLabelIndex, PCAdj); ARMPCLabelIndex, PCAdj);
SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
PseudoSourceValue::getConstantPool(), 0);
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
} }