[ARM GlobalISel] Support G_ICMP for Thumb2

Mark as legal and use the t2* equivalents of the arm mode instructions, e.g. t2CMPrr instead of plain CMPrr. llvm-svn: 353392
2019-02-07 11:05:33 +00:00 · 2019-02-07 11:05:33 +00:00 · 75a04e2a77
parent baf2f35ec4
commit 75a04e2a77
5 changed files with 461 additions and 104 deletions
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@ -97,6 +97,10 @@ private:
    unsigned STORE8;
    unsigned LOAD8;

+    unsigned CMPrr;
+    unsigned MOVi;
+    unsigned MOVCCi;
+
    OpcodeCache(const ARMSubtarget &STI);
  } const Opcodes;

@ -284,6 +288,10 @@ ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) {

  STORE_OPCODE(STORE8, STRBi12);
  STORE_OPCODE(LOAD8, LDRBi12);
+
+  STORE_OPCODE(CMPrr, CMPrr);
+  STORE_OPCODE(MOVi, MOVi);
+  STORE_OPCODE(MOVCCi, MOVCCi);
 #undef MAP_OPCODE
 }

@ -407,10 +415,11 @@ getComparePreds(CmpInst::Predicate Pred) {
 }

 struct ARMInstructionSelector::CmpConstants {
-  CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned OpRegBank,
-               unsigned OpSize)
+  CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned SelectOpcode,
+               unsigned OpRegBank, unsigned OpSize)
      : ComparisonOpcode(CmpOpcode), ReadFlagsOpcode(FlagsOpcode),
-        OperandRegBankID(OpRegBank), OperandSize(OpSize) {}
+        SelectResultOpcode(SelectOpcode), OperandRegBankID(OpRegBank),
+        OperandSize(OpSize) {}

  // The opcode used for performing the comparison.
  const unsigned ComparisonOpcode;
@ -419,6 +428,9 @@ struct ARMInstructionSelector::CmpConstants {
  // ARM::INSTRUCTION_LIST_END if we don't need to read the flags.
  const unsigned ReadFlagsOpcode;

+  // The opcode used for materializing the result of the comparison.
+  const unsigned SelectResultOpcode;
+
  // The assumed register bank ID for the operands.
  const unsigned OperandRegBankID;

@ -438,7 +450,7 @@ struct ARMInstructionSelector::InsertInfo {

 void ARMInstructionSelector::putConstant(InsertInfo I, unsigned DestReg,
                                         unsigned Constant) const {
-  (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVi))
+  (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Opcodes.MOVi))
      .addDef(DestReg)
      .addImm(Constant)
      .add(predOps(ARMCC::AL))
@ -541,7 +553,8 @@ bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I,
  }

  // Select either 1 or the previous result based on the value of the flags.
-  auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(ARM::MOVCCi))
+  auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
+                       TII.get(Helper.SelectResultOpcode))
                   .addDef(ResReg)
                   .addUse(PrevRes)
                   .addImm(1)
@ -899,8 +912,8 @@ bool ARMInstructionSelector::select(MachineInstr &I,
  case G_SELECT:
    return selectSelect(MIB, MRI);
  case G_ICMP: {
-    CmpConstants Helper(ARM::CMPrr, ARM::INSTRUCTION_LIST_END,
-                        ARM::GPRRegBankID, 32);
+    CmpConstants Helper(Opcodes.CMPrr, ARM::INSTRUCTION_LIST_END,
+                        Opcodes.MOVCCi, ARM::GPRRegBankID, 32);
    return selectCmp(Helper, MIB, MRI);
  }
  case G_FCMP: {
@ -919,7 +932,7 @@ bool ARMInstructionSelector::select(MachineInstr &I,
    }

    CmpConstants Helper(Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
-                        ARM::FPRRegBankID, Size);
+                        Opcodes.MOVCCi, ARM::FPRRegBankID, Size);
    return selectCmp(Helper, MIB, MRI);
  }
  case G_LSHR:
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@ -120,6 +120,10 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
      .legalFor({s32, p0})
      .clampScalar(0, s32, s32);

+  getActionDefinitionsBuilder(G_ICMP)
+      .legalForCartesianProduct({s1}, {s32, p0})
+      .minScalar(1, s32);
+
  // We're keeping these builders around because we'll want to add support for
  // floating point to them.
  auto &LoadStoreBuilder =
@ -168,10 +172,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {

  getActionDefinitionsBuilder(G_BRCOND).legalFor({s1});

-  getActionDefinitionsBuilder(G_ICMP)
-      .legalForCartesianProduct({s1}, {s32, p0})
-      .minScalar(1, s32);
-
  // We're keeping these builders around because we'll want to add support for
  // floating point to them.
  auto &PhiBuilder =
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-cmp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-cmp.mir
@ -0,0 +1,123 @@
+# RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
+--- |
+  define void @test_icmp_s8() { ret void }
+  define void @test_icmp_s16() { ret void }
+  define void @test_icmp_s32() { ret void }
+
+  define void @test_icmp_p0() { ret void }
+...
+---
+name:            test_icmp_s8
+# CHECK-LABEL: name: test_icmp_s8
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(p0) = COPY $r0
+    %1(s8) = G_LOAD %0 :: (load 1)
+    %2(p0) = COPY $r1
+    %3(s8) = G_LOAD %2 :: (load 1)
+    %4(s1) = G_ICMP intpred(ne), %1(s8), %3
+    ; G_ICMP with s8 should widen
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
+    %5(s32) = G_ZEXT %4(s1)
+    $r0 = COPY %5(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_s16
+# CHECK-LABEL: name: test_icmp_s16
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+  - { id: 4, class: _ }
+  - { id: 5, class: _ }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(p0) = COPY $r0
+    %1(s16) = G_LOAD %0 :: (load 2)
+    %2(p0) = COPY $r1
+    %3(s16) = G_LOAD %2 :: (load 2)
+    %4(s1) = G_ICMP intpred(slt), %1(s16), %3
+    ; G_ICMP with s16 should widen
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
+    %5(s32) = G_ZEXT %4(s1)
+    $r0 = COPY %5(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_s32
+# CHECK-LABEL: name: test_icmp_s32
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(eq), %0(s32), %1
+    ; G_ICMP with s32 is legal, so we should find it unchanged in the output
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_p0
+# CHECK-LABEL: name: test_icmp_p0
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    %0(p0) = COPY $r0
+    %1(p0) = COPY $r1
+    %2(s1) = G_ICMP intpred(eq), %0(p0), %1
+    ; G_ICMP with p0 is legal, so we should find it unchanged in the output
+    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(p0), {{%[0-9]+}}
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@ -5,10 +5,6 @@

  define void @test_constants_s64() { ret void }

-  define void @test_icmp_s8() { ret void }
-  define void @test_icmp_s16() { ret void }
-  define void @test_icmp_s32() { ret void }
-
  define void @test_select_s32() { ret void }
  define void @test_select_ptr() { ret void }

@ -112,94 +108,6 @@ body:             |
    BX_RET 14, $noreg
 ...
 ---
-name:            test_icmp_s8
-# CHECK-LABEL: name: test_icmp_s8
-legalized:       false
-# CHECK: legalized: true
-regBankSelected: false
-selected:        false
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
-  - { id: 5, class: _ }
-body:             |
-  bb.0:
-    liveins: $r0, $r1
-
-    %0(p0) = COPY $r0
-    %1(s8) = G_LOAD %0 :: (load 1)
-    %2(p0) = COPY $r1
-    %3(s8) = G_LOAD %2 :: (load 1)
-    %4(s1) = G_ICMP intpred(ne), %1(s8), %3
-    ; G_ICMP with s8 should widen
-    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
-    %5(s32) = G_ZEXT %4(s1)
-    $r0 = COPY %5(s32)
-    BX_RET 14, $noreg, implicit $r0
-...
---
-name:            test_icmp_s16
-# CHECK-LABEL: name: test_icmp_s16
-legalized:       false
-# CHECK: legalized: true
-regBankSelected: false
-selected:        false
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-  - { id: 4, class: _ }
-  - { id: 5, class: _ }
-body:             |
-  bb.0:
-    liveins: $r0, $r1
-
-    %0(p0) = COPY $r0
-    %1(s16) = G_LOAD %0 :: (load 2)
-    %2(p0) = COPY $r1
-    %3(s16) = G_LOAD %2 :: (load 2)
-    %4(s1) = G_ICMP intpred(slt), %1(s16), %3
-    ; G_ICMP with s16 should widen
-    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
-    ; CHECK-NOT: {{%[0-9]+}}:_(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
-    %5(s32) = G_ZEXT %4(s1)
-    $r0 = COPY %5(s32)
-    BX_RET 14, $noreg, implicit $r0
-...
---
-name:            test_icmp_s32
-# CHECK-LABEL: name: test_icmp_s32
-legalized:       false
-# CHECK: legalized: true
-regBankSelected: false
-selected:        false
-tracksRegLiveness: true
-registers:
-  - { id: 0, class: _ }
-  - { id: 1, class: _ }
-  - { id: 2, class: _ }
-  - { id: 3, class: _ }
-body:             |
-  bb.0:
-    liveins: $r0, $r1
-
-    %0(s32) = COPY $r0
-    %1(s32) = COPY $r1
-    %2(s1) = G_ICMP intpred(eq), %0(s32), %1
-    ; G_ICMP with s32 is legal, so we should find it unchanged in the output
-    ; CHECK: {{%[0-9]+}}:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), {{%[0-9]+}}
-    %3(s32) = G_ZEXT %2(s1)
-    $r0 = COPY %3(s32)
-    BX_RET 14, $noreg, implicit $r0
-...
---
 name:            test_select_s32
 # CHECK-LABEL: name: test_select_s32
 legalized:       false
--- a/llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir
@ -0,0 +1,313 @@
+# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+--- |
+  define void @test_icmp_eq_s32() { ret void }
+  define void @test_icmp_ne_s32() { ret void }
+  define void @test_icmp_ugt_s32() { ret void }
+  define void @test_icmp_uge_s32() { ret void }
+  define void @test_icmp_ult_s32() { ret void }
+  define void @test_icmp_ule_s32() { ret void }
+  define void @test_icmp_sgt_s32() { ret void }
+  define void @test_icmp_sge_s32() { ret void }
+  define void @test_icmp_slt_s32() { ret void }
+  define void @test_icmp_sle_s32() { ret void }
+...
+---
+name:            test_icmp_eq_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_eq_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 0, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(eq),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_ne_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_ne_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 1, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(ne),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_ugt_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_ugt_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 8, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(ugt),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_uge_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_uge_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 2, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(uge),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_ult_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_ult_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 3, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(ult),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_ule_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_ule_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 9, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(ule),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_sgt_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_sgt_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 12, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(sgt),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_sge_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_sge_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 10, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(sge),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_slt_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_slt_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 11, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(slt),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...
+---
+name:            test_icmp_sle_s32
+legalized:       true
+regBankSelected: true
+selected:        false
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+body:             |
+  bb.0:
+    liveins: $r0, $r1
+
+    ; CHECK-LABEL: name: test_icmp_sle_s32
+    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
+    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
+    ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg
+    ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr
+    ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 13, $cpsr
+    ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg
+    ; CHECK: $r0 = COPY [[ANDri]]
+    ; CHECK: BX_RET 14, $noreg, implicit $r0
+    %0(s32) = COPY $r0
+    %1(s32) = COPY $r1
+    %2(s1) = G_ICMP intpred(sle),  %0(s32), %1
+    %3(s32) = G_ZEXT %2(s1)
+    $r0 = COPY %3(s32)
+    BX_RET 14, $noreg, implicit $r0
+...