From 7563624fcba42032e95442bb4e8f439f5edf7669 Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Tue, 8 May 2018 09:50:37 +0000 Subject: [PATCH] [mips] Correct clo/clz predicates Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46125 llvm-svn: 331754 --- llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 4 +-- llvm/lib/Target/Mips/MipsInstrInfo.td | 37 ++++++++++------------ llvm/test/MC/Mips/micromips/valid.s | 2 ++ llvm/test/MC/Mips/mips32/valid.s | 2 ++ llvm/test/MC/Mips/mips32r2/valid.s | 2 ++ llvm/test/MC/Mips/mips32r3/valid.s | 2 ++ llvm/test/MC/Mips/mips32r5/valid.s | 2 ++ llvm/test/MC/Mips/mips32r6/valid.s | 2 ++ 8 files changed, 31 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index a16cc98e9c5e..1b0df6690cc0 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -921,9 +921,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Count Leading def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>, - ISA_MIPS32; + ISA_MICROMIPS; def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>, - ISA_MIPS32; + ISA_MICROMIPS; /// Sign Ext In Register Instructions. def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index ab5a13ac5872..37d6eb967404 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2279,27 +2279,24 @@ def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>, ISA_MIPS1_NOT_32R6_64R6; def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>, ISA_MIPS1_NOT_32R6_64R6; -let EncodingPredicates = [], // FIXME: Lack of HasStdEnc is probably a bug - AdditionalPredicates = [NotInMicroMips] in { -def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, - ISA_MIPS1_NOT_32R6_64R6; -def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, - ISA_MIPS1_NOT_32R6_64R6; - -/// Sign Ext In Register Instructions. -def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, - SEB_FM<0x10, 0x20>, ISA_MIPS32R2; -def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, - SEB_FM<0x18, 0x20>, ISA_MIPS32R2; -} - -/// Count Leading -def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, - ISA_MIPS32_NOT_32R6_64R6; -def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>, - ISA_MIPS32_NOT_32R6_64R6; - let AdditionalPredicates = [NotInMicroMips] in { + def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>, + ISA_MIPS1_NOT_32R6_64R6; + def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>, + ISA_MIPS1_NOT_32R6_64R6; + + /// Sign Ext In Register Instructions. + def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, + SEB_FM<0x10, 0x20>, ISA_MIPS32R2; + def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, + SEB_FM<0x18, 0x20>, ISA_MIPS32R2; + + /// Count Leading + def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>, + ISA_MIPS32_NOT_32R6_64R6; + def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>, + ISA_MIPS32_NOT_32R6_64R6; + /// Word Swap Bytes Within Halfwords def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>, ISA_MIPS32R2; diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index 73f3b7d8736e..654c21bd3a13 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -148,7 +148,9 @@ msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0x neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b] # CHECK-NEXT: #