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[mips] Correct clo/clz predicates 

Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46125

llvm-svn: 331754
This commit is contained in:
Simon Dardis 2018-05-08 09:50:37 +00:00
parent 3366dcfe1f
commit 7563624fcb
8 changed files with 31 additions and 22 deletions
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4
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
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@ -921,9 +921,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Count Leading
def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
ISA_MIPS32;
ISA_MICROMIPS;
def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
ISA_MIPS32;
ISA_MICROMIPS;
/// Sign Ext In Register Instructions.
def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,

37
llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -2279,27 +2279,24 @@ def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
ISA_MIPS1_NOT_32R6_64R6;
def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
ISA_MIPS1_NOT_32R6_64R6;
let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
AdditionalPredicates = [NotInMicroMips] in {
def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
ISA_MIPS1_NOT_32R6_64R6;
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
ISA_MIPS1_NOT_32R6_64R6;
/// Sign Ext In Register Instructions.
def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
}
/// Count Leading
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,
ISA_MIPS32_NOT_32R6_64R6;
def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>,
ISA_MIPS32_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
ISA_MIPS1_NOT_32R6_64R6;
def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
ISA_MIPS1_NOT_32R6_64R6;
/// Sign Ext In Register Instructions.
def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
/// Count Leading
def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,
ISA_MIPS32_NOT_32R6_64R6;
def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>,
ISA_MIPS32_NOT_32R6_64R6;
/// Word Swap Bytes Within Halfwords
def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
ISA_MIPS32R2;

2
llvm/test/MC/Mips/micromips/valid.s
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@ -148,7 +148,9 @@ msubu $4, $5 # CHECK: msubu $4, $5 # encoding: [0x00,0x
neg.d $f0, $f2 # CHECK: neg.d $f0, $f2 # encoding: [0x54,0x02,0x2b,0x7b]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} FNEG_D32_MM
clz $9, $6 # CHECK: clz $9, $6 # encoding: [0x01,0x26,0x5b,0x3c]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ_MM
clo $9, $6 # CHECK: clo $9, $6 # encoding: [0x01,0x26,0x4b,0x3c]
# CHECK-NEXT: # <MCInst #{{.*}} CLO_MM
seb $9, $6 # CHECK: seb $9, $6 # encoding: [0x01,0x26,0x2b,0x3c]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SEB_MM
seb $9 # CHECK: seb $9, $9 # encoding: [0x01,0x29,0x2b,0x3c]

2
llvm/test/MC/Mips/mips32/valid.s
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@ -80,7 +80,9 @@ a:
ceil.w.s $f6,$f20
cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
ctc1 $a2,$26
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S

2
llvm/test/MC/Mips/mips32r2/valid.s
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@ -80,7 +80,9 @@ a:
ceil.w.s $f6,$f20
cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
ctc1 $a2,$26
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S

2
llvm/test/MC/Mips/mips32r3/valid.s
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@ -80,7 +80,9 @@ a:
ceil.w.s $f6,$f20
cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
ctc1 $a2,$26
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S

2
llvm/test/MC/Mips/mips32r5/valid.s
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@ -80,7 +80,9 @@ a:
ceil.w.s $f6,$f20
cfc1 $s1,$21
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
ctc1 $a2,$26
cvt.d.s $f0,$f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} CVT_D32_S

2
llvm/test/MC/Mips/mips32r6/valid.s
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@ -197,7 +197,9 @@ a:
ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6]
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51]
# CHECK-NEXT: # <MCInst #{{.*}} CLO
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50]
# CHECK-NEXT: # <MCInst #{{.*}} CLZ
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]