parent
f924dd6f3c
commit
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@ -2617,10 +2617,9 @@ def : Pat <
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// Prevent expanding both fneg and fabs.
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// FIXME: Should use S_OR_B32
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def : Pat <
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(fneg (fabs f32:$src)),
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(V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
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(S_OR_B32 $src, 0x80000000) /* Set sign bit */
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>;
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// FIXME: Should use S_OR_B32
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@ -34,8 +34,7 @@ define void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) {
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @llvm.fabs.f32(float %bc)
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@ -49,8 +48,7 @@ define void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
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; R600: |PV.{{[XYZW]}}|
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; R600: -PV
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
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%bc = bitcast i32 %in to float
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%fabs = call float @fabs(float %bc)
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@ -60,8 +58,7 @@ define void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
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}
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; FUNC-LABEL: {{^}}fneg_fabs_f32:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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define void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
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%fabs = call float @llvm.fabs.f32(float %in)
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%fsub = fsub float -0.000000e+00, %fabs
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@ -85,11 +82,8 @@ define void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in)
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: -PV
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; FIXME: SGPR should be used directly for first src operand.
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-NOT: 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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%fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
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@ -97,14 +91,11 @@ define void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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ret void
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}
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; FIXME: SGPR should be used directly for first src operand.
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; FUNC-LABEL: {{^}}fneg_fabs_v4f32:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-NOT: 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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define void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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%fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
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