parent
7f74a56e24
commit
73da1cea60
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@ -996,7 +996,7 @@ void PhyRegAlloc::printMachineCode()
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}
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// if a label or a constant
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if(isa<BasicBlock>(Val) {
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if(isa<BasicBlock>(Val)) {
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cerr << "\t"; printLabel( Op.getVRegValue () );
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} else {
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// else it must be a register value
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