[Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute difference operation
This adds new intrinsics "*absdiff" for absolute difference ops to facilitate efficient code generation for "sum of absolute differences" operation. The patch also contains the introduction of corresponding SDNodes and basic legalization support.Sanity of the generated code is tested on X86. This is 1st of the three patches. Patch by Shahid Asghar-ahmad! llvm-svn: 242409
This commit is contained in:
James Molloy
parent
0e20b8dc93
commit
7395a8182c
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@ -10328,6 +10328,65 @@ Examples:
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%r2 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) ; yields float:r2 = (a * b) + c
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'``llvm.uabsdiff.*``' and '``llvm.sabsdiff.*``' Intrinsics
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic. The loaded data is a vector of any integer bit width.
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.. code-block:: llvm
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declare <4 x integer> @llvm.uabsdiff.v4i32(<4 x integer> %a, <4 x integer> %b)
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Overview:
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"""""""""
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The ``llvm.uabsdiff`` intrinsic returns a vector result of the absolute difference of the two operands,
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treating them both as unsigned integers.
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The ``llvm.sabsdiff`` intrinsic returns a vector result of the absolute difference of the two operands,
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treating them both as signed integers.
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.. note::
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These intrinsics are primarily used during the code generation stage of compilation.
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They are generated by compiler passes such as the Loop and SLP vectorizers.it is not
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recommended for users to create them manually.
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Arguments:
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""""""""""
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Both intrinsics take two integer of the same bitwidth.
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Semantics:
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""""""""""
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The expression::
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call <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32> %a, <4 x i32> %b)
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is equivalent to::
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%sub = sub <4 x i32> %a, %b
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%ispos = icmp ugt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32 -1>
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%neg = sub <4 x i32> zeroinitializer, %sub
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%1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg
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Similarly the expression::
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call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a, <4 x i32> %b)
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is equivalent to::
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%sub = sub nsw <4 x i32> %a, %b
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%ispos = icmp sgt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32 -1>
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%neg = sub nsw <4 x i32> zeroinitializer, %sub
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%1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg
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Half Precision Floating Point Intrinsics
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----------------------------------------
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@ -334,6 +334,10 @@ namespace ISD {
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/// Byte Swap and Counting operators.
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BSWAP, CTTZ, CTLZ, CTPOP,
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/// [SU]ABSDIFF - Signed/Unsigned absolute difference of two input integer
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/// vector. These nodes are generated from llvm.*absdiff* intrinsics.
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SABSDIFF, UABSDIFF,
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/// Bit counting operators with an undefined result for zero inputs.
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CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
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@ -605,6 +605,12 @@ def int_convertuu : Intrinsic<[llvm_anyint_ty],
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def int_clear_cache : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty],
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[], "llvm.clear_cache">;
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// Calculate the Absolute Differences of the two input vectors.
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def int_sabsdiff : Intrinsic<[llvm_anyvector_ty],
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[ LLVMMatchType<0>, LLVMMatchType<0> ], [IntrNoMem]>;
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def int_uabsdiff : Intrinsic<[llvm_anyvector_ty],
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[ LLVMMatchType<0>, LLVMMatchType<0> ], [IntrNoMem]>;
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//===-------------------------- Masked Intrinsics -------------------------===//
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//
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def int_masked_store : Intrinsic<[], [llvm_anyvector_ty, LLVMPointerTo<0>,
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@ -386,6 +386,8 @@ def smax : SDNode<"ISD::SMAX" , SDTIntBinOp>;
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def umin : SDNode<"ISD::UMIN" , SDTIntBinOp>;
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def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;
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def sabsdiff : SDNode<"ISD::SABSDIFF" , SDTIntBinOp>;
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def uabsdiff : SDNode<"ISD::UABSDIFF" , SDTIntBinOp>;
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def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
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def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
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def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
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@ -146,6 +146,10 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
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case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
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Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
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break;
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case ISD::UABSDIFF:
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case ISD::SABSDIFF:
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Res = PromoteIntRes_SimpleIntBinOp(N);
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break;
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}
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// If the result is null then the sub-method took care of registering it.
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@ -105,6 +105,7 @@ class VectorLegalizer {
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SDValue ExpandLoad(SDValue Op);
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SDValue ExpandStore(SDValue Op);
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SDValue ExpandFNEG(SDValue Op);
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SDValue ExpandABSDIFF(SDValue Op);
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/// \brief Implements vector promotion.
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///
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@ -326,6 +327,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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case ISD::SMAX:
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case ISD::UMIN:
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case ISD::UMAX:
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case ISD::UABSDIFF:
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case ISD::SABSDIFF:
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QueryType = Node->getValueType(0);
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break;
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case ISD::FP_ROUND_INREG:
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@ -708,11 +711,36 @@ SDValue VectorLegalizer::Expand(SDValue Op) {
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return ExpandFNEG(Op);
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case ISD::SETCC:
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return UnrollVSETCC(Op);
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case ISD::UABSDIFF:
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case ISD::SABSDIFF:
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return ExpandABSDIFF(Op);
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default:
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return DAG.UnrollVectorOp(Op.getNode());
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}
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}
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SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) {
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SDLoc dl(Op);
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SDValue Tmp1, Tmp2, Tmp3, Tmp4;
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EVT VT = Op.getValueType();
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SDNodeFlags Flags;
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Flags.setNoSignedWrap(Op->getOpcode() == ISD::SABSDIFF);
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Tmp2 = Op.getOperand(0);
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Tmp3 = Op.getOperand(1);
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Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp3, &Flags);
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Tmp2 =
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DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Tmp1, &Flags);
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Tmp4 = DAG.getNode(
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ISD::SETCC, dl,
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TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Tmp2,
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DAG.getConstant(0, dl, VT),
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DAG.getCondCode(Op->getOpcode() == ISD::SABSDIFF ? ISD::SETLT
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: ISD::SETULT));
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Tmp1 = DAG.getNode(ISD::VSELECT, dl, VT, Tmp4, Tmp1, Tmp2);
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return Tmp1;
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}
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SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
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// Lower a select instruction where the condition is a scalar and the
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// operands are vectors. Lower this select to VSELECT and implement it
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@ -678,6 +678,8 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::SMAX:
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case ISD::UMIN:
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case ISD::UMAX:
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case ISD::UABSDIFF:
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case ISD::SABSDIFF:
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SplitVecRes_BinOp(N, Lo, Hi);
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break;
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case ISD::FMA:
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@ -4646,6 +4646,18 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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getValue(I.getArgOperand(0)).getValueType(),
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getValue(I.getArgOperand(0))));
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return nullptr;
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case Intrinsic::uabsdiff:
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setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
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getValue(I.getArgOperand(0)).getValueType(),
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getValue(I.getArgOperand(0)),
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getValue(I.getArgOperand(1))));
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return nullptr;
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case Intrinsic::sabsdiff:
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setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
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getValue(I.getArgOperand(0)).getValueType(),
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getValue(I.getArgOperand(0)),
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getValue(I.getArgOperand(1))));
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return nullptr;
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case Intrinsic::cttz: {
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SDValue Arg = getValue(I.getArgOperand(0));
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ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
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@ -225,6 +225,8 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
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case ISD::SHL_PARTS: return "shl_parts";
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case ISD::SRA_PARTS: return "sra_parts";
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case ISD::SRL_PARTS: return "srl_parts";
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case ISD::UABSDIFF: return "uabsdiff";
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case ISD::SABSDIFF: return "sabsdiff";
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// Conversion operators.
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case ISD::SIGN_EXTEND: return "sign_extend";
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@ -827,6 +827,8 @@ void TargetLoweringBase::initActions() {
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setOperationAction(ISD::USUBO, VT, Expand);
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setOperationAction(ISD::SMULO, VT, Expand);
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setOperationAction(ISD::UMULO, VT, Expand);
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setOperationAction(ISD::UABSDIFF, VT, Expand);
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setOperationAction(ISD::SABSDIFF, VT, Expand);
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// These library functions default to expand.
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setOperationAction(ISD::FROUND, VT, Expand);
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@ -0,0 +1,242 @@
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK
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declare <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8>, <4 x i8>)
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define <4 x i8> @test_uabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8> %a2) {
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; CHECK-LABEL: test_uabsdiff_v4i8_expand
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; CHECK: psubd %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: psubd %xmm0, %xmm1
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; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}
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; CHECK-NEXT: movdqa %xmm1, %xmm3
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; CHECK-NEXT: pxor %xmm2, %xmm3
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; CHECK-NEXT: pcmpgtd %xmm3, %xmm2
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; CHECK-NEXT: pand %xmm2, %xmm0
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; CHECK-NEXT: pandn %xmm1, %xmm2
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; CHECK-NEXT: por %xmm2, %xmm0
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; CHECK-NEXT: retq
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%1 = call <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)
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ret <4 x i8> %1
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}
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declare <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8>, <4 x i8>)
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define <4 x i8> @test_sabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8> %a2) {
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; CHECK-LABEL: test_sabsdiff_v4i8_expand
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; CHECK: psubd %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pxor %xmm2, %xmm2
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; CHECK-NEXT: psubd %xmm0, %xmm2
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; CHECK-NEXT: pcmpgtd %xmm2, %xmm1
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; CHECK-NEXT: pand %xmm1, %xmm0
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; CHECK-NEXT: pandn %xmm2, %xmm1
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = call <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)
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ret <4 x i8> %1
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}
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declare <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8>, <8 x i8>)
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define <8 x i8> @test_sabsdiff_v8i8_expand(<8 x i8> %a1, <8 x i8> %a2) {
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; CHECK-LABEL: test_sabsdiff_v8i8_expand
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; CHECK: psubw %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pxor %xmm2, %xmm2
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; CHECK-NEXT: psubw %xmm0, %xmm2
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; CHECK-NEXT: pcmpgtw %xmm2, %xmm1
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; CHECK-NEXT: pand %xmm1, %xmm0
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; CHECK-NEXT: pandn %xmm2, %xmm1
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = call <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8> %a1, <8 x i8> %a2)
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ret <8 x i8> %1
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}
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declare <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8>, <16 x i8>)
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define <16 x i8> @test_uabsdiff_v16i8_expand(<16 x i8> %a1, <16 x i8> %a2) {
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; CHECK-LABEL: test_uabsdiff_v16i8_expand
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; CHECK: psubb %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: psubb %xmm0, %xmm1
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; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}
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; CHECK-NEXT: movdqa %xmm1, %xmm3
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; CHECK-NEXT: pxor %xmm2, %xmm3
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; CHECK-NEXT: pcmpgtb %xmm3, %xmm2
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; CHECK-NEXT: pand %xmm2, %xmm0
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; CHECK-NEXT: pandn %xmm1, %xmm2
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; CHECK-NEXT: por %xmm2, %xmm0
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; CHECK-NEXT: retq
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%1 = call <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8> %a1, <16 x i8> %a2)
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ret <16 x i8> %1
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}
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declare <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_uabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16> %a2) {
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; CHECK-LABEL: test_uabsdiff_v8i16_expand
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; CHECK: psubw %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: psubw %xmm0, %xmm1
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; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}
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; CHECK-NEXT: movdqa %xmm1, %xmm3
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; CHECK-NEXT: pxor %xmm2, %xmm3
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; CHECK-NEXT: pcmpgtw %xmm3, %xmm2
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; CHECK-NEXT: pand %xmm2, %xmm0
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; CHECK-NEXT: pandn %xmm1, %xmm2
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; CHECK-NEXT: por %xmm2, %xmm0
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; CHECK-NEXT: retq
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%1 = call <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16> %a1, <8 x i16> %a2)
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ret <8 x i16> %1
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}
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declare <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16>, <8 x i16>)
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define <8 x i16> @test_sabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16> %a2) {
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; CHECK-LABEL: test_sabsdiff_v8i16_expand
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; CHECK: psubw %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pxor %xmm2, %xmm2
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; CHECK-NEXT: psubw %xmm0, %xmm2
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; CHECK-NEXT: pcmpgtw %xmm2, %xmm1
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; CHECK-NEXT: pand %xmm1, %xmm0
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; CHECK-NEXT: pandn %xmm2, %xmm1
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = call <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16> %a1, <8 x i16> %a2)
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ret <8 x i16> %1
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}
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declare <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_sabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32> %a2) {
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; CHECK-LABEL: test_sabsdiff_v4i32_expand
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; CHECK: psubd %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pxor %xmm2, %xmm2
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; CHECK-NEXT: psubd %xmm0, %xmm2
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; CHECK-NEXT: pcmpgtd %xmm2, %xmm1
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; CHECK-NEXT: pand %xmm1, %xmm0
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; CHECK-NEXT: pandn %xmm2, %xmm1
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a1, <4 x i32> %a2)
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ret <4 x i32> %1
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}
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declare <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32>, <4 x i32>)
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define <4 x i32> @test_uabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32> %a2) {
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; CHECK-LABEL: test_uabsdiff_v4i32_expand
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; CHECK: psubd %xmm1, %xmm0
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: psubd %xmm0, %xmm1
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; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}
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; CHECK-NEXT: movdqa %xmm1, %xmm3
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; CHECK-NEXT: pxor %xmm2, %xmm3
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; CHECK-NEXT: pcmpgtd %xmm3, %xmm2
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; CHECK-NEXT: pand %xmm2, %xmm0
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; CHECK-NEXT: pandn %xmm1, %xmm2
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; CHECK-NEXT: por %xmm2, %xmm0
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; CHECK-NEXT: retq
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%1 = call <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32> %a1, <4 x i32> %a2)
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ret <4 x i32> %1
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}
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declare <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32>, <2 x i32>)
|
||||
|
||||
define <2 x i32> @test_sabsdiff_v2i32_expand(<2 x i32> %a1, <2 x i32> %a2) {
|
||||
; CHECK-LABEL: test_sabsdiff_v2i32_expand
|
||||
; CHECK: psubq %xmm1, %xmm0
|
||||
; CHECK-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-NEXT: psubq %xmm0, %xmm1
|
||||
; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}
|
||||
; CHECK-NEXT: movdqa %xmm1, %xmm3
|
||||
; CHECK-NEXT: pxor %xmm2, %xmm3
|
||||
; CHECK-NEXT: movdqa %xmm2, %xmm4
|
||||
; CHECK-NEXT: pcmpgtd %xmm3, %xmm4
|
||||
; CHECK-NEXT: pshufd $160, %xmm4, %xmm5 # xmm5 = xmm4[0,0,2,2]
|
||||
; CHECK-NEXT: pcmpeqd %xmm2, %xmm3
|
||||
; CHECK-NEXT: pshufd $245, %xmm3, %xmm2 # xmm2 = xmm3[1,1,3,3]
|
||||
; CHECK-NEXT: pand %xmm5, %xmm2
|
||||
; CHECK-NEXT: pshufd $245, %xmm4, %xmm3 # xmm3 = xmm4[1,1,3,3]
|
||||
; CHECK-NEXT: por %xmm2, %xmm3
|
||||
; CHECK-NEXT: pand %xmm3, %xmm0
|
||||
; CHECK-NEXT: pandn %xmm1, %xmm3
|
||||
; CHECK-NEXT: por %xmm3, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%1 = call <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32> %a1, <2 x i32> %a2)
|
||||
ret <2 x i32> %1
|
||||
}
|
||||
|
||||
declare <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64>, <2 x i64>)
|
||||
|
||||
define <2 x i64> @test_sabsdiff_v2i64_expand(<2 x i64> %a1, <2 x i64> %a2) {
|
||||
; CHECK-LABEL: test_sabsdiff_v2i64_expand
|
||||
; CHECK: psubq %xmm1, %xmm0
|
||||
; CHECK-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-NEXT: psubq %xmm0, %xmm1
|
||||
; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}
|
||||
; CHECK-NEXT: movdqa %xmm1, %xmm3
|
||||
; CHECK-NEXT: pxor %xmm2, %xmm3
|
||||
; CHECK-NEXT: movdqa %xmm2, %xmm4
|
||||
; CHECK-NEXT: pcmpgtd %xmm3, %xmm4
|
||||
; CHECK-NEXT: pshufd $160, %xmm4, %xmm5 # xmm5 = xmm4[0,0,2,2]
|
||||
; CHECK-NEXT: pcmpeqd %xmm2, %xmm3
|
||||
; CHECK-NEXT: pshufd $245, %xmm3, %xmm2 # xmm2 = xmm3[1,1,3,3]
|
||||
; CHECK-NEXT: pand %xmm5, %xmm2
|
||||
; CHECK-NEXT: pshufd $245, %xmm4, %xmm3 # xmm3 = xmm4[1,1,3,3]
|
||||
; CHECK-NEXT: por %xmm2, %xmm3
|
||||
; CHECK-NEXT: pand %xmm3, %xmm0
|
||||
; CHECK-NEXT: pandn %xmm1, %xmm3
|
||||
; CHECK-NEXT: por %xmm3, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
%1 = call <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64> %a1, <2 x i64> %a2)
|
||||
ret <2 x i64> %1
|
||||
}
|
||||
|
||||
declare <16 x i32> @llvm.sabsdiff.v16i32(<16 x i32>, <16 x i32>)
|
||||
|
||||
define <16 x i32> @test_sabsdiff_v16i32_expand(<16 x i32> %a1, <16 x i32> %a2) {
|
||||
; CHECK-LABEL: test_sabsdiff_v16i32_expand
|
||||
; CHECK: psubd %xmm4, %xmm0
|
||||
; CHECK-NEXT: pxor %xmm8, %xmm8
|
||||
; CHECK-NEXT: pxor %xmm9, %xmm9
|
||||
; CHECK-NEXT: psubd %xmm0, %xmm9
|
||||
; CHECK-NEXT: pxor %xmm4, %xmm4
|
||||
; CHECK-NEXT: pcmpgtd %xmm9, %xmm4
|
||||
; CHECK-NEXT: pand %xmm4, %xmm0
|
||||
; CHECK-NEXT: pandn %xmm9, %xmm4
|
||||
; CHECK-NEXT: por %xmm4, %xmm0
|
||||
; CHECK-NEXT: psubd %xmm5, %xmm1
|
||||
; CHECK-NEXT: pxor %xmm4, %xmm4
|
||||
; CHECK-NEXT: psubd %xmm1, %xmm4
|
||||
; CHECK-NEXT: pxor %xmm5, %xmm5
|
||||
; CHECK-NEXT: pcmpgtd %xmm4, %xmm5
|
||||
; CHECK-NEXT: pand %xmm5, %xmm1
|
||||
; CHECK-NEXT: pandn %xmm4, %xmm5
|
||||
; CHECK-NEXT: por %xmm5, %xmm1
|
||||
; CHECK-NEXT: psubd %xmm6, %xmm2
|
||||
; CHECK-NEXT: pxor %xmm4, %xmm4
|
||||
; CHECK-NEXT: psubd %xmm2, %xmm4
|
||||
; CHECK-NEXT: pxor %xmm5, %xmm5
|
||||
; CHECK-NEXT: pcmpgtd %xmm4, %xmm5
|
||||
; CHECK-NEXT: pand %xmm5, %xmm2
|
||||
; CHECK-NEXT: pandn %xmm4, %xmm5
|
||||
; CHECK-NEXT: por %xmm5, %xmm2
|
||||
; CHECK-NEXT: psubd %xmm7, %xmm3
|
||||
; CHECK-NEXT: pxor %xmm4, %xmm4
|
||||
; CHECK-NEXT: psubd %xmm3, %xmm4
|
||||
; CHECK-NEXT: pcmpgtd %xmm4, %xmm8
|
||||
; CHECK-NEXT: pand %xmm8, %xmm3
|
||||
; CHECK-NEXT: pandn %xmm4, %xmm8
|
||||
; CHECK-NEXT: por %xmm8, %xmm3
|
||||
; CHECK-NEXT: retq
|
||||
%1 = call <16 x i32> @llvm.sabsdiff.v16i32(<16 x i32> %a1, <16 x i32> %a2)
|
||||
ret <16 x i32> %1
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue