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[X86] Move some EVEX->VEX code to a helper function to prepare for a future patch. NFC 

llvm-svn: 316881
This commit is contained in:
Craig Topper 2017-10-30 03:35:43 +00:00
parent 27f95a9ac3
commit 730414b0ca
1 changed files with 33 additions and 24 deletions
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57
llvm/lib/Target/X86/X86EvexToVex.cpp
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@ -132,6 +132,38 @@ void EvexToVexInstPass::AddTableEntry(EvexToVexTableType &EvexToVexTable,
EvexToVexTable[EvexOp] = VexOp;
}
static bool usesExtendedRegister(const MachineInstr &MI) {
auto isHiRegIdx = [](unsigned Reg) {
// Check for XMM register with indexes between 16 - 31.
if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
return true;
// Check for YMM register with indexes between 16 - 31.
if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
return true;
return false;
};
// Check that operands are not ZMM regs or
// XMM/YMM regs with hi indexes between 16 - 31.
for (const MachineOperand &MO : MI.explicit_operands()) {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
assert(!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31) &&
"ZMM instructions should not be in the EVEX->VEX tables");
if (isHiRegIdx(Reg))
return true;
}
return false;
}
// For EVEX instructions that can be encoded using VEX encoding
// replace them by the VEX encoding in order to reduce size.
bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
@ -188,31 +220,8 @@ bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
if (!NewOpc)
return false;
auto isHiRegIdx = [](unsigned Reg) {
// Check for XMM register with indexes between 16 - 31.
if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
return true;
// Check for YMM register with indexes between 16 - 31.
if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
return true;
if (usesExtendedRegister(MI))
return false;
};
// Check that operands are not ZMM regs or
// XMM/YMM regs with hi indexes between 16 - 31.
for (const MachineOperand &MO : MI.explicit_operands()) {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
assert (!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31));
if (isHiRegIdx(Reg))
return false;
}
const MCInstrDesc &MCID = TII->get(NewOpc);
MI.setDesc(MCID);