Added several SPARC instructions including conditional move and SETHI.
Added MachineInstrInfo class and subclass UltraSparcInstrInfo. Added several fields to MachineInstrDescriptor (and renamed it from MachineInstrInfo). Latency fields are to support scheduling. llvm-svn: 313
This commit is contained in:
Vikram S. Adve
parent
f72a942a3c
commit
72ffa4357c
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@ -21,24 +21,9 @@ const OpCodeMask Annul = 0x20000000; // annul delay instr?
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const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
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//---------------------------------------------------------------------------
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// class UltraSparcMachine
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//
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// Purpose:
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// Machine description.
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//
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//---------------------------------------------------------------------------
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class UltraSparc: public TargetMachine {
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public:
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/*ctor*/ UltraSparc ();
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/*dtor*/ virtual ~UltraSparc () {}
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};
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//---------------------------------------------------------------------------
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// enum SparcMachineOpCode.
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// const MachineInstrInfo SparcMachineInstrInfo[].
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// const MachineInstrDescriptor SparcMachineInstrDesc[]
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//
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// Purpose:
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// Description of UltraSparc machine instructions.
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@ -54,6 +39,9 @@ enum SparcMachineOpCode {
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SETSW,
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SETUW,
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// Set high-order bits of register and clear low-order bits
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SETHI,
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// Add or add with carry.
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// Immed bit specifies if second operand is immediate(1) or register(0)
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ADD,
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@ -192,6 +180,53 @@ enum SparcMachineOpCode {
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FBULE,
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FBO,
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// Conditional move on integer comparison with zero.
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MOVRZ,
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MOVRLEZ,
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MOVRLZ,
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MOVRNZ,
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MOVRGZ,
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MOVRGEZ,
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// Conditional move on integer condition code.
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MOVA,
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MOVN,
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MOVNE,
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MOVE,
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MOVG,
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MOVLE,
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MOVGE,
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MOVL,
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MOVGU,
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MOVLEU,
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MOVCC,
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MOVCS,
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MOVPOS,
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MOVNEG,
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MOVVC,
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MOVVS,
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// Conditional move on floating point condition code.
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// Note that the enum name is not the same as the assembly mnemonic below
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// because that would duplicate some entries with those above.
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// Therefore, we use MOVF here instead of MOV.
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MOVFA,
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MOVFN,
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MOVFU,
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MOVFG,
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MOVFUG,
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MOVFL,
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MOVFUL,
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MOVFLG,
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MOVFNE,
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MOVFE,
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MOVFUE,
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MOVFGE,
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MOVFUGE,
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MOVFLE,
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MOVFULE,
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MOVFO,
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// Load integer instructions
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LDSB,
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LDSH,
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@ -226,178 +261,304 @@ enum SparcMachineOpCode {
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INVALID_OPCODE
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};
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const MachineInstrInfo SparcMachineInstrInfo[] = {
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const MachineInstrDescriptor SparcMachineInstrDesc[] = {
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{ "NOP", 0, -1, 0, false },
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// Fields of each structure:
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// opCodeString,
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// numOperands,
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// resultPosition (0-based; -1 if no result),
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// maxImmedConst,
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// immedIsSignExtended,
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// numDelaySlots (in cycles)
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// latency (in cycles)
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// class flags
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// Synthetic SPARC assembly opcodes for setting a register to a constant
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{ "SETSW", 2, 1, 0, true }, // max immediate constant is ignored
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{ "SETUW", 2, 1, 0, false }, // max immediate constant is ignored
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{ "NOP", 0, -1, 0, false, 0, 1, M_NOP_FLAG },
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// Synthetic SPARC assembly opcodes for setting a register to a constant.
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// Max immediate constant should be ignored for both these instructions.
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{ "SETSW", 2, 1, 0, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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{ "SETUW", 2, 1, 0, false, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG },
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// Set high-order bits of register and clear low-order bits
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{ "SETHI", 2, 1, (1 << 22) - 1, false, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG },
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// Add or add with carry.
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{ "ADD", 3, 2, (1 << 12) - 1, true },
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{ "ADDcc", 3, 2, (1 << 12) - 1, true },
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{ "ADDC", 3, 2, (1 << 12) - 1, true },
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{ "ADDCcc", 3, 2, (1 << 12) - 1, true },
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{ "ADD", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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{ "ADDcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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{ "ADDC", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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{ "ADDCcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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// Sub tract or subtract with carry.
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{ "SUB", 3, 2, (1 << 12) - 1, true },
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{ "SUBcc", 3, 2, (1 << 12) - 1, true },
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{ "SUBC", 3, 2, (1 << 12) - 1, true },
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{ "SUBCcc", 3, 2, (1 << 12) - 1, true },
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{ "SUB", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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{ "SUBcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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{ "SUBC", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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{ "SUBCcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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// Integer multiply, signed divide, unsigned divide.
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// Note that the deprecated 32-bit multiply and multiply-step are not used.
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{ "MULX", 3, 2, (1 << 12) - 1, true },
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{ "SDIVX", 3, 2, (1 << 12) - 1, true },
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{ "UDIVX", 3, 2, (1 << 12) - 1, true },
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{ "MULX", 3, 2, (1 << 12) - 1, true, 0, 3, M_INT_FLAG | M_ARITH_FLAG },
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{ "SDIVX", 3, 2, (1 << 12) - 1, true, 0, 6, M_INT_FLAG | M_ARITH_FLAG },
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{ "UDIVX", 3, 2, (1 << 12) - 1, true, 0, 6, M_INT_FLAG | M_ARITH_FLAG },
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// Floating point add, subtract, compare
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{ "FADDS", 3, 2, 0, false },
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{ "FADDD", 3, 2, 0, false },
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{ "FADDQ", 3, 2, 0, false },
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{ "FSUBS", 3, 2, 0, false },
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{ "FSUBD", 3, 2, 0, false },
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{ "FSUBQ", 3, 2, 0, false },
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{ "FCMPS", 3, 2, 0, false },
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{ "FCMPD", 3, 2, 0, false },
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{ "FCMPQ", 3, 2, 0, false },
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// Floating point add, subtract, compare.
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// Note that destination of FCMP* instructions is operand 0, not operand 2.
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{ "FADDS", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FADDD", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FADDQ", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FSUBS", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FSUBD", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FSUBQ", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FCMPS", 3, 0, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FCMPD", 3, 0, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FCMPQ", 3, 0, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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// NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
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// Floating point multiply or divide.
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{ "FMULS", 3, 2, 0, false },
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{ "FMULD", 3, 2, 0, false },
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{ "FMULQ", 3, 2, 0, false },
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{ "FSMULD", 3, 2, 0, false },
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{ "FDMULQ", 3, 2, 0, false },
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{ "FDIVS", 3, 2, 0, false },
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{ "FDIVD", 3, 2, 0, false },
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{ "FDIVQ", 3, 2, 0, false },
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{ "FMULS", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FMULD", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FMULQ", 3, 2, 0, false, 0, 0, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FSMULD", 3, 2, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FDMULQ", 3, 2, 0, false, 0, 0, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FDIVS", 3, 2, 0, false, 0, 22, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FDIVD", 3, 2, 0, false, 0, 22, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FDIVQ", 3, 2, 0, false, 0, 0, M_FLOAT_FLAG | M_ARITH_FLAG },
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// Logical operations
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{ "AND", 3, 2, (1 << 12) - 1, true },
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{ "ANDcc", 3, 2, (1 << 12) - 1, true },
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{ "ANDN", 3, 2, (1 << 12) - 1, true },
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{ "ANDNcc", 3, 2, (1 << 12) - 1, true },
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{ "OR", 3, 2, (1 << 12) - 1, true },
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{ "ORcc", 3, 2, (1 << 12) - 1, true },
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{ "ORN", 3, 2, (1 << 12) - 1, true },
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{ "ORNcc", 3, 2, (1 << 12) - 1, true },
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{ "XOR", 3, 2, (1 << 12) - 1, true },
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{ "XORcc", 3, 2, (1 << 12) - 1, true },
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{ "XNOR", 3, 2, (1 << 12) - 1, true },
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{ "XNORcc", 3, 2, (1 << 12) - 1, true },
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{ "AND", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "ANDcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "ANDN", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "ANDNcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "OR", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "ORcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "ORN", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "ORNcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "XOR", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "XORcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "XNOR", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "XNORcc", 3, 2, (1 << 12) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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// Shift operations
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{ "SLL", 3, 2, (1 << 5) - 1, true },
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{ "SRL", 3, 2, (1 << 5) - 1, true },
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{ "SRA", 3, 2, (1 << 5) - 1, true },
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{ "SLLX", 3, 2, (1 << 6) - 1, true },
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{ "SRLX", 3, 2, (1 << 6) - 1, true },
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{ "SRAX", 3, 2, (1 << 6) - 1, true },
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{ "SLL", 3, 2, (1 << 5) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "SRL", 3, 2, (1 << 5) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "SRA", 3, 2, (1 << 5) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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{ "SLLX", 3, 2, (1 << 6) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "SRLX", 3, 2, (1 << 6) - 1, true, 0, 1, M_INT_FLAG | M_LOGICAL_FLAG},
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{ "SRAX", 3, 2, (1 << 6) - 1, true, 0, 1, M_INT_FLAG | M_ARITH_FLAG },
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// Convert from floating point to floating point formats
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{ "FSTOD", 2, 1, 0, false },
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{ "FSTOQ", 2, 1, 0, false },
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{ "FDTOS", 2, 1, 0, false },
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{ "FDTOQ", 2, 1, 0, false },
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{ "FQTOS", 2, 1, 0, false },
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{ "FQTOD", 2, 1, 0, false },
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{ "FSTOD", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FSTOQ", 2, 1, 0, false, 0, 0, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FDTOS", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FDTOQ", 2, 1, 0, false, 0, 0, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FQTOS", 2, 1, 0, false, 0, 0, M_FLOAT_FLAG | M_ARITH_FLAG },
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{ "FQTOD", 2, 1, 0, false, 0, 0, M_FLOAT_FLAG | M_ARITH_FLAG },
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// Convert from floating point to integer formats
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{ "FSTOX", 2, 1, 0, false },
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{ "FDTOX", 2, 1, 0, false },
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{ "FQTOX", 2, 1, 0, false },
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{ "FSTOI", 2, 1, 0, false },
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{ "FDTOI", 2, 1, 0, false },
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{ "FQTOI", 2, 1, 0, false },
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// Convert from floating point to integer formats.
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// Note that this accesses both integer and floating point registers.
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{ "FSTOX", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FDTOX", 2, 1, 0, false, 0, 0, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FQTOX", 2, 1, 0, false, 0, 2, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FSTOI", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FDTOI", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FQTOI", 2, 1, 0, false, 0, 0, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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// Convert from integer to floating point formats
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{ "FXTOS", 2, 1, 0, false },
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{ "FXTOD", 2, 1, 0, false },
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{ "FXTOQ", 2, 1, 0, false },
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{ "FITOS", 2, 1, 0, false },
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{ "FITOD", 2, 1, 0, false },
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{ "FITOQ", 2, 1, 0, false },
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// Note that this accesses both integer and floating point registers.
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{ "FXTOS", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FXTOD", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FXTOQ", 2, 1, 0, false, 0, 0, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FITOS", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FITOD", 2, 1, 0, false, 0, 3, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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{ "FITOQ", 2, 1, 0, false, 0, 0, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
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// Branch on integer comparison with zero.
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{ "BRZ", 2, -1, (1 << 15) - 1, true },
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{ "BRLEZ", 2, -1, (1 << 15) - 1, true },
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{ "BRLZ", 2, -1, (1 << 15) - 1, true },
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{ "BRNZ", 2, -1, (1 << 15) - 1, true },
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{ "BRGZ", 2, -1, (1 << 15) - 1, true },
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{ "BRGEZ", 2, -1, (1 << 15) - 1, true },
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// Latency includes the delay slot.
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{ "BRZ", 2, -1, (1 << 15) - 1, true, 1, 2, M_INT_FLAG | M_BRANCH_FLAG },
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{ "BRLEZ", 2, -1, (1 << 15) - 1, true, 1, 2, M_INT_FLAG | M_BRANCH_FLAG },
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{ "BRLZ", 2, -1, (1 << 15) - 1, true, 1, 2, M_INT_FLAG | M_BRANCH_FLAG },
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{ "BRNZ", 2, -1, (1 << 15) - 1, true, 1, 2, M_INT_FLAG | M_BRANCH_FLAG },
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{ "BRGZ", 2, -1, (1 << 15) - 1, true, 1, 2, M_INT_FLAG | M_BRANCH_FLAG },
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{ "BRGEZ", 2, -1, (1 << 15) - 1, true, 1, 2, M_INT_FLAG | M_BRANCH_FLAG },
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// Branch on condition code.
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{ "BA", 1, -1, (1 << 21) - 1, true },
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{ "BN", 1, -1, (1 << 21) - 1, true },
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{ "BNE", 1, -1, (1 << 21) - 1, true },
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{ "BE", 1, -1, (1 << 21) - 1, true },
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{ "BG", 1, -1, (1 << 21) - 1, true },
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{ "BLE", 1, -1, (1 << 21) - 1, true },
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{ "BGE", 1, -1, (1 << 21) - 1, true },
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{ "BL", 1, -1, (1 << 21) - 1, true },
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{ "BGU", 1, -1, (1 << 21) - 1, true },
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{ "BLEU", 1, -1, (1 << 21) - 1, true },
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{ "BCC", 1, -1, (1 << 21) - 1, true },
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{ "BCS", 1, -1, (1 << 21) - 1, true },
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{ "BPOS", 1, -1, (1 << 21) - 1, true },
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{ "BNEG", 1, -1, (1 << 21) - 1, true },
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{ "BVC", 1, -1, (1 << 21) - 1, true },
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{ "BVS", 1, -1, (1 << 21) - 1, true },
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// The first argument specifies the ICC register: %icc or %xcc
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// Latency includes the delay slot.
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{ "BA", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
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{ "BN", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
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{ "BNE", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
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{ "BE", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
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{ "BG", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
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{ "BLE", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
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{ "BGE", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
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||||
{ "BL", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "BGU", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "BLEU", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "BCC", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "BCS", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "BPOS", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "BNEG", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "BVC", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "BVS", 2, -1, (1 << 21) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
|
||||
// Branch on floating point condition code.
|
||||
// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
|
||||
// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
|
||||
// The first argument is the FCCn register (0 <= n <= 3).
|
||||
{ "FBA", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBN", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBU", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBG", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBUG", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBL", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBUL", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBLG", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBNE", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBE", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBUE", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBGE", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBUGE", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBLE", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBULE", 2, -1, (1 << 18) - 1, true },
|
||||
{ "FBO", 2, -1, (1 << 18) - 1, true },
|
||||
// Latency includes the delay slot.
|
||||
{ "FBA", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBN", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBU", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBG", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBUG", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBL", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBUL", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBLG", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBNE", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBE", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBUE", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBGE", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBUGE", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBLE", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBULE", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
{ "FBO", 2, -1, (1 << 18) - 1, true, 1, 2, M_CC_FLAG | M_BRANCH_FLAG },
|
||||
|
||||
// Conditional move on integer comparison with zero.
|
||||
{ "MOVRZ", 3, 2, (1 << 12) - 1, true, 0, 1, M_CONDL_FLAG | M_INT_FLAG },
|
||||
{ "MOVRLEZ", 3, 2, (1 << 12) - 1, true, 0, 1, M_CONDL_FLAG | M_INT_FLAG },
|
||||
{ "MOVRLZ", 3, 2, (1 << 12) - 1, true, 0, 1, M_CONDL_FLAG | M_INT_FLAG },
|
||||
{ "MOVRNZ", 3, 2, (1 << 12) - 1, true, 0, 1, M_CONDL_FLAG | M_INT_FLAG },
|
||||
{ "MOVRGZ", 3, 2, (1 << 12) - 1, true, 0, 1, M_CONDL_FLAG | M_INT_FLAG },
|
||||
{ "MOVRGEZ", 3, 2, (1 << 12) - 1, true, 0, 1, M_CONDL_FLAG | M_INT_FLAG },
|
||||
|
||||
// Conditional move on integer condition code.
|
||||
// The first argument specifies the ICC register: %icc or %xcc
|
||||
{ "MOVA", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVN", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVNE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVG", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVLE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVGE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVL", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVGU", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVLEU", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVCC", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVCS", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVPOS", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVNEG", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVVC", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVVS", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
|
||||
// Conditional move (of integer register) on floating point condition code.
|
||||
// The first argument is the FCCn register (0 <= n <= 3).
|
||||
// Note that the enum name above is not the same as the assembly mnemonic
|
||||
// because some of the assembly mnemonics are the same as the move on
|
||||
// integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
|
||||
{ "MOVA", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVN", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVU", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVG", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVUG", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVL", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVUL", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVLG", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVNE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVUE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVGE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVUGE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVLE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVULE", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
{ "MOVO", 3, 2, (1 << 12) - 1, true, 0, 1, M_CC_FLAG | M_INT_FLAG },
|
||||
|
||||
// Load integer instructions
|
||||
{ "LDSB", 3, 2, (1 << 12) - 1, true },
|
||||
{ "LDSH", 3, 2, (1 << 12) - 1, true },
|
||||
{ "LDSW", 3, 2, (1 << 12) - 1, true },
|
||||
{ "LDUB", 3, 2, (1 << 12) - 1, true },
|
||||
{ "LDUH", 3, 2, (1 << 12) - 1, true },
|
||||
{ "LDUW", 3, 2, (1 << 12) - 1, true },
|
||||
{ "LDX", 3, 2, (1 << 12) - 1, true },
|
||||
// Latency includes 1 cycle for address generation (Sparc IIi)
|
||||
// Signed loads of less than 64 bits need an extra cycle for sign-extension.
|
||||
//
|
||||
// Not reflected here: After a 3-cycle loads, all subsequent consecutive
|
||||
// loads also require 3 cycles to avoid contention for the load return
|
||||
// stage. Latency returns to 2 cycles after the first cycle with no load.
|
||||
{ "LDSB", 3, 2, (1 << 12) - 1, true, 0, 3, M_INT_FLAG | M_LOAD_FLAG },
|
||||
{ "LDSH", 3, 2, (1 << 12) - 1, true, 0, 3, M_INT_FLAG | M_LOAD_FLAG },
|
||||
{ "LDSW", 3, 2, (1 << 12) - 1, true, 0, 3, M_INT_FLAG | M_LOAD_FLAG },
|
||||
{ "LDUB", 3, 2, (1 << 12) - 1, true, 0, 2, M_INT_FLAG | M_LOAD_FLAG },
|
||||
{ "LDUH", 3, 2, (1 << 12) - 1, true, 0, 2, M_INT_FLAG | M_LOAD_FLAG },
|
||||
{ "LDUW", 3, 2, (1 << 12) - 1, true, 0, 2, M_INT_FLAG | M_LOAD_FLAG },
|
||||
{ "LDX", 3, 2, (1 << 12) - 1, true, 0, 2, M_INT_FLAG | M_LOAD_FLAG },
|
||||
|
||||
// Load floating-point instructions
|
||||
{ "LD", 3, 2, (1 << 12) - 1, true },
|
||||
{ "LDD", 3, 2, (1 << 12) - 1, true },
|
||||
{ "LDQ", 3, 2, (1 << 12) - 1, true },
|
||||
// Latency includes 1 cycle for address generation (Sparc IIi)
|
||||
{ "LD", 3, 2, (1 << 12) - 1, true, 0, 2, M_FLOAT_FLAG | M_LOAD_FLAG },
|
||||
{ "LDD", 3, 2, (1 << 12) - 1, true, 0, 2, M_FLOAT_FLAG | M_LOAD_FLAG },
|
||||
{ "LDQ", 3, 2, (1 << 12) - 1, true, 0, 2, M_FLOAT_FLAG | M_LOAD_FLAG },
|
||||
|
||||
// Store integer instructions
|
||||
{ "STB", 3, -1, (1 << 12) - 1, true },
|
||||
{ "STH", 3, -1, (1 << 12) - 1, true },
|
||||
{ "STW", 3, -1, (1 << 12) - 1, true },
|
||||
{ "STX", 3, -1, (1 << 12) - 1, true },
|
||||
// Latency includes 1 cycle for address generation (Sparc IIi)
|
||||
{ "STB", 3, -1, (1 << 12) - 1, true, 0, 2, M_INT_FLAG | M_STORE_FLAG },
|
||||
{ "STH", 3, -1, (1 << 12) - 1, true, 0, 2, M_INT_FLAG | M_STORE_FLAG },
|
||||
{ "STW", 3, -1, (1 << 12) - 1, true, 0, 2, M_INT_FLAG | M_STORE_FLAG },
|
||||
{ "STX", 3, -1, (1 << 12) - 1, true, 0, 3, M_INT_FLAG | M_STORE_FLAG },
|
||||
|
||||
// Store floating-point instructions
|
||||
{ "ST", 3, -1, (1 << 12) - 1, true },
|
||||
{ "STD", 3, -1, (1 << 12) - 1, true },
|
||||
// Store floating-point instructions (Sparc IIi)
|
||||
{ "ST", 3, -1, (1 << 12) - 1, true, 0, 2, M_FLOAT_FLAG | M_STORE_FLAG},
|
||||
{ "STD", 3, -1, (1 << 12) - 1, true, 0, 2, M_FLOAT_FLAG | M_STORE_FLAG},
|
||||
|
||||
// Call, Return and "Jump and link"
|
||||
{ "CALL", 1, -1, (1 << 29) - 1, true },
|
||||
{ "JMPL", 3, -1, (1 << 12) - 1, true },
|
||||
{ "RETURN", 2, -1, 0, false },
|
||||
// Call, Return and "Jump and link".
|
||||
// Latency includes the delay slot.
|
||||
{ "CALL", 1, -1, (1 << 29) - 1, true, 1, 2, M_BRANCH_FLAG | M_CALL_FLAG},
|
||||
{ "JMPL", 3, -1, (1 << 12) - 1, true, 1, 2, M_BRANCH_FLAG | M_CALL_FLAG},
|
||||
{ "RETURN", 2, -1, 0, false, 1, 2, M_BRANCH_FLAG | M_RET_FLAG },
|
||||
|
||||
// End-of-array marker
|
||||
{ "INVALID_SPARC_OPCODE", 0, -1, 0, false }
|
||||
{ "INVALID_SPARC_OPCODE", 0, -1, 0, false, 0, 0, 0x0 }
|
||||
};
|
||||
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// class UltraSparcInstrInfo
|
||||
//
|
||||
// Purpose:
|
||||
// Information about individual instructions.
|
||||
// Most information is stored in the SparcMachineInstrDesc array above.
|
||||
// Other information is computed on demand, and most such functions
|
||||
// default to member functions in base class MachineInstrInfo.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
class UltraSparcInstrInfo : public MachineInstrInfo {
|
||||
public:
|
||||
/*ctor*/ UltraSparcInstrInfo()
|
||||
: MachineInstrInfo(SparcMachineInstrDesc, INVALID_OPCODE)
|
||||
{}
|
||||
|
||||
virtual bool hasResultInterlock (MachineOpCode opCode)
|
||||
{
|
||||
// All UltraSPARC instructions have interlocks (note that delay slots
|
||||
// are not considered here).
|
||||
// However, instructions that use the result of an FCMP produce a
|
||||
// 9-cycle stall if they are issued less than 3 cycles after the FCMP.
|
||||
// Force the compiler to insert a software interlock (i.e., gap of
|
||||
// 2 other groups, including NOPs if necessary).
|
||||
return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// class UltraSparcMachine
|
||||
//
|
||||
// Purpose:
|
||||
// Primary interface to machine description for the UltraSPARC.
|
||||
// Primarily just initializes machine-dependent parameters in
|
||||
// class TargetMachine, and creates machine-dependent subclasses
|
||||
// for classes such as MachineInstrInfo.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
class UltraSparc: public TargetMachine {
|
||||
public:
|
||||
/*ctor*/ UltraSparc ();
|
||||
/*dtor*/ virtual ~UltraSparc ();
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue