[AArch64][GlobalISel] Select immediate modes for ADD when selecting G_GEP
Before, we weren't able to select things like this for G_GEP: add x0, x8, #8 And instead we'd materialize the 8. This teaches GISel to do that. It gives some considerable code size savings on 252.eon-- about 4%! Differential Revision: https://reviews.llvm.org/D65248 llvm-svn: 366959
This commit is contained in:
Jessica Paquette
parent
75c64a66c1
commit
728b18f29f
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@ -133,6 +133,8 @@ private:
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MachineInstr *emitIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
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MachineOperand &Predicate,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitCMN(MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitTST(const Register &LHS, const Register &RHS,
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@ -1829,8 +1831,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return selectVectorSHL(I, MRI);
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LLVM_FALLTHROUGH;
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case TargetOpcode::G_OR:
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case TargetOpcode::G_LSHR:
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case TargetOpcode::G_GEP: {
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case TargetOpcode::G_LSHR: {
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// Reject the various things we don't support yet.
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if (unsupportedBinOp(I, RBI, MRI, TRI))
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return false;
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@ -1852,6 +1853,13 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
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}
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case TargetOpcode::G_GEP: {
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MachineIRBuilder MIRBuilder(I);
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emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2),
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MIRBuilder);
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I.eraseFromParent();
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return true;
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}
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case TargetOpcode::G_UADDO: {
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// TODO: Support other types.
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unsigned OpSize = Ty.getSizeInBits();
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@ -3080,6 +3088,31 @@ getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
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return std::make_pair(Opc, SubregIdx);
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}
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MachineInstr *
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AArch64InstructionSelector::emitADD(Register DefReg, MachineOperand &LHS,
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MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const {
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assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
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MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
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static const unsigned OpcTable[2][2]{{AArch64::ADDXrr, AArch64::ADDXri},
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{AArch64::ADDWrr, AArch64::ADDWri}};
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bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32;
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auto ImmFns = selectArithImmed(RHS);
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unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
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auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS.getReg()});
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// If we matched a valid constant immediate, add those operands.
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if (ImmFns) {
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for (auto &RenderFn : *ImmFns)
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RenderFn(AddMI);
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} else {
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AddMI.addUse(RHS.getReg());
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}
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constrainSelectedInstRegOperands(*AddMI, TII, TRI, RBI);
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return &*AddMI;
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}
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MachineInstr *
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AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const {
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@ -11,6 +11,8 @@
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}
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define i8* @gep(i8* %in) { ret i8* undef }
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define i8* @gep_no_constant(i8* %in) { ret i8* undef }
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define i8* @gep_bad_imm(i8* %in) { ret i8* undef }
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define i8* @ptr_mask(i8* %in) { ret i8* undef }
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@ -61,8 +63,7 @@ registers:
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- { id: 2, class: gpr }
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# CHECK: body:
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# CHECK: %1:gpr64 = MOVi64imm 42
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# CHECK: %2:gpr64 = ADDXrr %0, %1
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# CHECK: %2:gpr64sp = ADDXri %0, 42, 0
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body: |
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bb.0:
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liveins: $x0
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@ -72,6 +73,52 @@ body: |
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$x0 = COPY %2(p0)
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...
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---
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# CHECK-LABEL: name: gep_no_constant
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name: gep_no_constant
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# CHECK: body:
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# CHECK: %0:gpr64 = COPY $x0
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# CHECK: %1:gpr64 = COPY $x1
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# CHECK: %2:gpr64 = ADDXrr %0, %1
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body: |
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bb.0:
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liveins: $x0, $x1
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%0(p0) = COPY $x0
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%1(s64) = COPY $x1
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%2(p0) = G_GEP %0, %1(s64)
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$x0 = COPY %2(p0)
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...
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---
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# CHECK-LABEL: name: gep_bad_imm
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name: gep_bad_imm
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# CHECK: body:
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# CHECK: %0:gpr64 = COPY $x0
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# CHECK: %1:gpr64 = MOVi64imm 10000
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# CHECK: %2:gpr64 = ADDXrr %0, %1
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body: |
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bb.0:
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liveins: $x0, $x1
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%0(p0) = COPY $x0
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%1(s64) = G_CONSTANT i64 10000
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%2(p0) = G_GEP %0, %1(s64)
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$x0 = COPY %2(p0)
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...
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---
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# CHECK-LABEL: name: ptr_mask
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name: ptr_mask
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@ -226,14 +226,11 @@ define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) {
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; CHECK-DAG: strb [[ID]], [x0, #8]
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; First vararg
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; CHECK: ldr {{w[0-9]+}}, [x[[ARG1:[0-9]+]]]
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; CHECK: ldr {{w[0-9]+}}, [x[[ARG1:[0-9]+]]], #8
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; Second vararg
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; CHECK: mov [[EIGHT:x[0-9]+]], #8
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; CHECK: add x[[ARG2:[0-9]+]], x[[ARG1]], [[EIGHT]]
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; CHECK: ldr {{w[0-9]+}}, [x[[ARG2]]]
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; CHECK: ldr {{w[0-9]+}}, [x[[ARG1]]], #8
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; Third vararg
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; CHECK: add x[[ARG3:[0-9]+]], x[[ARG2]], [[EIGHT]]
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; CHECK: ldr {{w[0-9]+}}, [x[[ARG3]]]
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; CHECK: ldr {{w[0-9]+}}, [x[[ARG1]]], #8
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; CHECK: mov x21, x0
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; CHECK-NOT: x21
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