* Introduce a new SelectionDAG::getIntPtrConstant method
and switch various codegen pieces and the X86 backend over to using it. * Add some comments to SelectionDAGNodes.h * Introduce a second argument to FP_ROUND, which indicates whether the FP_ROUND changes the value of its input. If not it is safe to xform things like fp_extend(fp_round(x)) -> x. llvm-svn: 46125
This commit is contained in:
parent
89126bde19
commit
72733e573b
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@ -177,6 +177,7 @@ public:
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//
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//
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SDOperand getString(const std::string &Val);
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SDOperand getString(const std::string &Val);
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SDOperand getConstant(uint64_t Val, MVT::ValueType VT, bool isTarget = false);
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SDOperand getConstant(uint64_t Val, MVT::ValueType VT, bool isTarget = false);
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SDOperand getIntPtrConstant(uint64_t Val, bool isTarget = false);
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SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT) {
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SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT) {
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return getConstant(Val, VT, true);
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return getConstant(Val, VT, true);
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}
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}
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@ -385,13 +385,22 @@ namespace ISD {
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// operand, a ValueType node.
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// operand, a ValueType node.
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SIGN_EXTEND_INREG,
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SIGN_EXTEND_INREG,
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// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
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/// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
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// integer.
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/// integer.
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FP_TO_SINT,
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FP_TO_SINT,
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FP_TO_UINT,
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FP_TO_UINT,
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// FP_ROUND - Perform a rounding operation from the current
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/// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
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// precision down to the specified precision (currently always 64->32).
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/// down to the precision of the destination VT. TRUNC is a flag, which is
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/// always an integer that is zero or one. If TRUNC is 0, this is a
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/// normal rounding, if it is 1, this FP_ROUND is known to not change the
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/// value of Y.
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///
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/// The TRUNC = 1 case is used in cases where we know that the value will
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/// not be modified by the node, because Y is not using any of the extra
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/// precision of source type. This allows certain transformations like
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/// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
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/// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
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FP_ROUND,
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FP_ROUND,
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// FLT_ROUNDS - Returns current rounding mode:
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// FLT_ROUNDS - Returns current rounding mode:
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@ -402,14 +411,14 @@ namespace ISD {
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// 3 Round to -inf
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// 3 Round to -inf
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FLT_ROUNDS,
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FLT_ROUNDS,
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// FP_ROUND_INREG - This operator takes a floating point register, and
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/// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
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// rounds it to a floating point value. It then promotes it and returns it
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/// rounds it to a floating point value. It then promotes it and returns it
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// in a register of the same size. This operation effectively just discards
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/// in a register of the same size. This operation effectively just
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// excess precision. The type to round down to is specified by the 1th
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/// discards excess precision. The type to round down to is specified by
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// operation, a VTSDNode (currently always 64->32->64).
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/// the VT operand, a VTSDNode.
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FP_ROUND_INREG,
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FP_ROUND_INREG,
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// FP_EXTEND - Extend a smaller FP type into a larger FP type.
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/// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
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FP_EXTEND,
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FP_EXTEND,
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// BIT_CONVERT - Theis operator converts between integer and FP values, as
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// BIT_CONVERT - Theis operator converts between integer and FP values, as
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@ -135,6 +135,7 @@ namespace {
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SDOperand To[] = { Res0, Res1 };
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SDOperand To[] = { Res0, Res1 };
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return CombineTo(N, To, 2, AddTo);
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return CombineTo(N, To, 2, AddTo);
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}
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}
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private:
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private:
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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/// SimplifyDemandedBits - Check the specified integer node value to see if
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@ -460,10 +461,13 @@ static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
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GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
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GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
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case ISD::FP_EXTEND:
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case ISD::FP_EXTEND:
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case ISD::FP_ROUND:
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case ISD::FSIN:
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case ISD::FSIN:
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return DAG.getNode(Op.getOpcode(), Op.getValueType(),
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return DAG.getNode(Op.getOpcode(), Op.getValueType(),
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GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
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GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
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case ISD::FP_ROUND:
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return DAG.getNode(ISD::FP_ROUND, Op.getValueType(),
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GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
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Op.getOperand(1));
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}
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}
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}
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}
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@ -3632,12 +3636,13 @@ SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
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SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
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SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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SDOperand N0 = N->getOperand(0);
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SDOperand N1 = N->getOperand(1);
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ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
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ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
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MVT::ValueType VT = N->getValueType(0);
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MVT::ValueType VT = N->getValueType(0);
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// fold (fp_round c1fp) -> c1fp
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// fold (fp_round c1fp) -> c1fp
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if (N0CFP && N0.getValueType() != MVT::ppcf128)
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if (N0CFP && N0.getValueType() != MVT::ppcf128)
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return DAG.getNode(ISD::FP_ROUND, VT, N0);
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return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
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// fold (fp_round (fp_extend x)) -> x
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// fold (fp_round (fp_extend x)) -> x
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if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
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if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
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@ -3645,7 +3650,7 @@ SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
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// fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
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// fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
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if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
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if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
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SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
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SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
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AddToWorkList(Tmp.Val);
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AddToWorkList(Tmp.Val);
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return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
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return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
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}
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}
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@ -3680,7 +3685,17 @@ SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
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if (N0CFP && VT != MVT::ppcf128)
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if (N0CFP && VT != MVT::ppcf128)
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return DAG.getNode(ISD::FP_EXTEND, VT, N0);
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return DAG.getNode(ISD::FP_EXTEND, VT, N0);
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// fold (fpext (load x)) -> (fpext (fpround (extload x)))
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// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
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// value of X.
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if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){
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SDOperand In = N0.getOperand(0);
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if (In.getValueType() == VT) return In;
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if (VT < In.getValueType())
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return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
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return DAG.getNode(ISD::FP_EXTEND, VT, In);
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}
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// fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
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if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
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if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
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(!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
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(!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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@ -3691,7 +3706,8 @@ SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
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LN0->isVolatile(),
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LN0->isVolatile(),
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LN0->getAlignment());
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LN0->getAlignment());
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CombineTo(N, ExtLoad);
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CombineTo(N, ExtLoad);
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CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
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CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad,
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DAG.getIntPtrConstant(1)),
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ExtLoad.getValue(1));
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ExtLoad.getValue(1));
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return SDOperand(N, 0); // Return N so it doesn't get rechecked!
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return SDOperand(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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@ -4435,13 +4451,11 @@ SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
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// Otherwise, use InIdx + VecSize
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// Otherwise, use InIdx + VecSize
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unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
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unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
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BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
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BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
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TLI.getPointerTy()));
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}
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}
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// Add count and size info.
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// Add count and size info.
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MVT::ValueType BuildVecVT =
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MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts);
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MVT::getVectorType(TLI.getPointerTy(), NumElts);
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// Return the new VECTOR_SHUFFLE node.
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// Return the new VECTOR_SHUFFLE node.
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SDOperand Ops[5];
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SDOperand Ops[5];
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@ -220,10 +220,6 @@ private:
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SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
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SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
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SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
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SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
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SDOperand getIntPtrConstant(uint64_t Val) {
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return DAG.getConstant(Val, TLI.getPointerTy());
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}
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};
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};
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}
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}
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@ -2123,7 +2119,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
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Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
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SVOffset, isVolatile, Alignment);
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SVOffset, isVolatile, Alignment);
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Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
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Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
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getIntPtrConstant(4));
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DAG.getIntPtrConstant(4));
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Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
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Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
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isVolatile, MinAlign(Alignment, 4U));
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isVolatile, MinAlign(Alignment, 4U));
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@ -2186,8 +2182,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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if (MVT::isVector(ST->getValue().getValueType())) {
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if (MVT::isVector(ST->getValue().getValueType())) {
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SDNode *InVal = ST->getValue().Val;
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SDNode *InVal = ST->getValue().Val;
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int InIx = ST->getValue().ResNo;
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int InIx = ST->getValue().ResNo;
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unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
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MVT::ValueType InVT = InVal->getValueType(InIx);
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MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
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unsigned NumElems = MVT::getVectorNumElements(InVT);
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MVT::ValueType EVT = MVT::getVectorElementType(InVT);
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// Figure out if there is a simple type corresponding to this Vector
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// Figure out if there is a simple type corresponding to this Vector
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// type. If so, convert to the vector type.
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// type. If so, convert to the vector type.
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@ -2231,7 +2228,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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}
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}
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Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
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Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
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getIntPtrConstant(IncrementSize));
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DAG.getIntPtrConstant(IncrementSize));
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assert(isTypeLegal(Tmp2.getValueType()) &&
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assert(isTypeLegal(Tmp2.getValueType()) &&
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"Pointers must be legal!");
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"Pointers must be legal!");
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SVOffset += IncrementSize;
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SVOffset += IncrementSize;
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@ -2429,7 +2426,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
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Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
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// Perform the larger operation, then round down.
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// Perform the larger operation, then round down.
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
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Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
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if (TruncOp != ISD::FP_ROUND)
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Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
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Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
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else
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Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
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DAG.getIntPtrConstant(0));
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break;
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break;
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}
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}
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}
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}
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@ -3496,13 +3497,13 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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MVT::ValueType OVT = Node->getOperand(0).getValueType();
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MVT::ValueType OVT = Node->getOperand(0).getValueType();
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// Convert ppcf128 to i32
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// Convert ppcf128 to i32
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if (OVT == MVT::ppcf128 && VT == MVT::i32) {
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if (OVT == MVT::ppcf128 && VT == MVT::i32) {
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if (Node->getOpcode()==ISD::FP_TO_SINT)
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if (Node->getOpcode() == ISD::FP_TO_SINT) {
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Result = DAG.getNode(ISD::FP_TO_SINT, VT,
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Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
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DAG.getNode(ISD::FP_ROUND, MVT::f64,
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Node->getOperand(0), DAG.getValueType(MVT::f64));
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(DAG.getNode(ISD::FP_ROUND_INREG,
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Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
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MVT::ppcf128, Node->getOperand(0),
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DAG.getIntPtrConstant(1));
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DAG.getValueType(MVT::f64)))));
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Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
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else {
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} else {
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const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
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const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
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APFloat apf = APFloat(APInt(128, 2, TwoE31));
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APFloat apf = APFloat(APInt(128, 2, TwoE31));
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Tmp2 = DAG.getConstantFP(apf, OVT);
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Tmp2 = DAG.getConstantFP(apf, OVT);
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@ -3581,7 +3582,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
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Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
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break;
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break;
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}
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}
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}
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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switch (getTypeAction(Node->getOperand(0).getValueType())) {
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case Expand: assert(0 && "Shouldn't need to expand other operators here!");
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case Expand: assert(0 && "Shouldn't need to expand other operators here!");
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case Legal:
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case Legal:
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@ -3594,6 +3594,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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break;
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break;
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}
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}
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break;
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break;
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}
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case ISD::FP_ROUND: {
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case ISD::FP_ROUND: {
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MVT::ValueType DstVT = Op.getValueType();
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MVT::ValueType DstVT = Op.getValueType();
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MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
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MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
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@ -3601,28 +3602,29 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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if (SrcVT == MVT::ppcf128) {
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if (SrcVT == MVT::ppcf128) {
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SDOperand Lo, Hi;
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SDOperand Lo, Hi;
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ExpandOp(Node->getOperand(0), Lo, Hi);
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ExpandOp(Node->getOperand(0), Lo, Hi);
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Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi);
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// Round it the rest of the way (e.g. to f32) if needed.
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Result = DAG.getNode(ISD::FP_ROUND, DstVT, Hi, Op.getOperand(1));
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break;
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break;
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} else {
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}
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// The only other way we can lower this is to turn it into a STORE,
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// The only other way we can lower this is to turn it into a STORE,
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// LOAD pair, targetting a temporary location (a stack slot).
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// LOAD pair, targetting a temporary location (a stack slot).
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Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
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Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
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break;
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break;
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}
|
}
|
||||||
}
|
|
||||||
}
|
|
||||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||||
case Expand: assert(0 && "Shouldn't need to expand other operators here!");
|
case Expand: assert(0 && "Shouldn't need to expand other operators here!");
|
||||||
case Legal:
|
case Legal:
|
||||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
Tmp1 = LegalizeOp(Node->getOperand(0));
|
||||||
Result = DAG.UpdateNodeOperands(Result, Tmp1);
|
Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
|
||||||
break;
|
break;
|
||||||
case Promote:
|
case Promote:
|
||||||
Tmp1 = PromoteOp(Node->getOperand(0));
|
Tmp1 = PromoteOp(Node->getOperand(0));
|
||||||
Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1);
|
Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
|
||||||
|
Node->getOperand(1));
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
case ISD::ANY_EXTEND:
|
case ISD::ANY_EXTEND:
|
||||||
case ISD::ZERO_EXTEND:
|
case ISD::ZERO_EXTEND:
|
||||||
case ISD::SIGN_EXTEND:
|
case ISD::SIGN_EXTEND:
|
||||||
|
@ -3869,13 +3871,18 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
|
||||||
case Expand: assert(0 && "BUG: Cannot expand FP regs!");
|
case Expand: assert(0 && "BUG: Cannot expand FP regs!");
|
||||||
case Promote: assert(0 && "Unreachable with 2 FP types!");
|
case Promote: assert(0 && "Unreachable with 2 FP types!");
|
||||||
case Legal:
|
case Legal:
|
||||||
|
if (Node->getConstantOperandVal(1) == 0) {
|
||||||
// Input is legal? Do an FP_ROUND_INREG.
|
// Input is legal? Do an FP_ROUND_INREG.
|
||||||
Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
|
Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
|
||||||
DAG.getValueType(VT));
|
DAG.getValueType(VT));
|
||||||
|
} else {
|
||||||
|
// Just remove the truncate, it isn't affecting the value.
|
||||||
|
Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
|
||||||
|
Node->getOperand(1));
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case ISD::SINT_TO_FP:
|
case ISD::SINT_TO_FP:
|
||||||
case ISD::UINT_TO_FP:
|
case ISD::UINT_TO_FP:
|
||||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||||
|
@ -4028,24 +4035,14 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
|
||||||
case ISD::FCOPYSIGN:
|
case ISD::FCOPYSIGN:
|
||||||
// These operators require that their input be fp extended.
|
// These operators require that their input be fp extended.
|
||||||
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
switch (getTypeAction(Node->getOperand(0).getValueType())) {
|
||||||
case Legal:
|
case Expand: assert(0 && "not implemented");
|
||||||
Tmp1 = LegalizeOp(Node->getOperand(0));
|
case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
|
||||||
break;
|
case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
|
||||||
case Promote:
|
|
||||||
Tmp1 = PromoteOp(Node->getOperand(0));
|
|
||||||
break;
|
|
||||||
case Expand:
|
|
||||||
assert(0 && "not implemented");
|
|
||||||
}
|
}
|
||||||
switch (getTypeAction(Node->getOperand(1).getValueType())) {
|
switch (getTypeAction(Node->getOperand(1).getValueType())) {
|
||||||
case Legal:
|
case Expand: assert(0 && "not implemented");
|
||||||
Tmp2 = LegalizeOp(Node->getOperand(1));
|
case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
|
||||||
break;
|
case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
|
||||||
case Promote:
|
|
||||||
Tmp2 = PromoteOp(Node->getOperand(1));
|
|
||||||
break;
|
|
||||||
case Expand:
|
|
||||||
assert(0 && "not implemented");
|
|
||||||
}
|
}
|
||||||
Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
|
Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
|
||||||
|
|
||||||
|
@ -4978,7 +4975,7 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
|
||||||
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
|
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
|
||||||
DAG.getConstant(0, Hi.getValueType()),
|
DAG.getConstant(0, Hi.getValueType()),
|
||||||
ISD::SETLT);
|
ISD::SETLT);
|
||||||
SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
|
SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
|
||||||
SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
|
SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
|
||||||
SignSet, Four, Zero);
|
SignSet, Four, Zero);
|
||||||
uint64_t FF = 0x5f800000ULL;
|
uint64_t FF = 0x5f800000ULL;
|
||||||
|
@ -5100,7 +5097,8 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
|
||||||
// do nothing
|
// do nothing
|
||||||
Result = Sub;
|
Result = Sub;
|
||||||
} else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
|
} else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
|
||||||
Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
|
Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
|
||||||
|
DAG.getIntPtrConstant(0));
|
||||||
} else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
|
} else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
|
||||||
Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
|
Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
|
||||||
}
|
}
|
||||||
|
@ -5112,7 +5110,7 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
|
||||||
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
|
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
|
||||||
DAG.getConstant(0, Op0.getValueType()),
|
DAG.getConstant(0, Op0.getValueType()),
|
||||||
ISD::SETLT);
|
ISD::SETLT);
|
||||||
SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
|
SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
|
||||||
SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
|
SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
|
||||||
SignSet, Four, Zero);
|
SignSet, Four, Zero);
|
||||||
|
|
||||||
|
@ -5570,7 +5568,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||||
// Increment the pointer to the other half.
|
// Increment the pointer to the other half.
|
||||||
unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
|
unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
SVOffset += IncrementSize;
|
SVOffset += IncrementSize;
|
||||||
Alignment = MinAlign(Alignment, IncrementSize);
|
Alignment = MinAlign(Alignment, IncrementSize);
|
||||||
Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
|
Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
|
||||||
|
@ -6523,7 +6521,7 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
|
||||||
Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
|
Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
|
||||||
unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
|
unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
SVOffset += IncrementSize;
|
SVOffset += IncrementSize;
|
||||||
Alignment = MinAlign(Alignment, IncrementSize);
|
Alignment = MinAlign(Alignment, IncrementSize);
|
||||||
Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
|
Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
|
||||||
|
|
|
@ -82,10 +82,6 @@ class VISIBILITY_HIDDEN DAGTypeLegalizer {
|
||||||
return getTypeAction(VT) == Legal;
|
return getTypeAction(VT) == Legal;
|
||||||
}
|
}
|
||||||
|
|
||||||
SDOperand getIntPtrConstant(uint64_t Val) {
|
|
||||||
return DAG.getConstant(Val, TLI.getPointerTy());
|
|
||||||
}
|
|
||||||
|
|
||||||
/// PromotedNodes - For nodes that are below legal width, this map indicates
|
/// PromotedNodes - For nodes that are below legal width, this map indicates
|
||||||
/// what promoted value to use.
|
/// what promoted value to use.
|
||||||
DenseMap<SDOperand, SDOperand> PromotedNodes;
|
DenseMap<SDOperand, SDOperand> PromotedNodes;
|
||||||
|
|
|
@ -253,7 +253,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
|
||||||
// Increment the pointer to the other half.
|
// Increment the pointer to the other half.
|
||||||
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
|
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
Hi = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
||||||
isVolatile, MinAlign(Alignment, IncrementSize));
|
isVolatile, MinAlign(Alignment, IncrementSize));
|
||||||
|
|
||||||
|
@ -300,7 +300,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
|
||||||
// Increment the pointer to the other half.
|
// Increment the pointer to the other half.
|
||||||
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
|
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
|
Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
|
||||||
SVOffset+IncrementSize, NEVT,
|
SVOffset+IncrementSize, NEVT,
|
||||||
isVolatile, MinAlign(Alignment, IncrementSize));
|
isVolatile, MinAlign(Alignment, IncrementSize));
|
||||||
|
@ -324,7 +324,7 @@ void DAGTypeLegalizer::ExpandResult_LOAD(LoadSDNode *N,
|
||||||
|
|
||||||
// Increment the pointer to the other half.
|
// Increment the pointer to the other half.
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
// Load the rest of the low bits.
|
// Load the rest of the low bits.
|
||||||
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
|
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
|
||||||
SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits),
|
SVOffset+IncrementSize, MVT::getIntegerType(ExcessBits),
|
||||||
|
@ -869,7 +869,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_UINT_TO_FP(SDOperand Source,
|
||||||
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
|
SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
|
||||||
DAG.getConstant(0, Hi.getValueType()),
|
DAG.getConstant(0, Hi.getValueType()),
|
||||||
ISD::SETLT);
|
ISD::SETLT);
|
||||||
SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
|
SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
|
||||||
SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
|
SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
|
||||||
SignSet, Four, Zero);
|
SignSet, Four, Zero);
|
||||||
uint64_t FF = 0x5f800000ULL;
|
uint64_t FF = 0x5f800000ULL;
|
||||||
|
@ -1053,7 +1053,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
|
||||||
SVOffset, isVolatile, Alignment);
|
SVOffset, isVolatile, Alignment);
|
||||||
|
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
|
assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
|
||||||
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
||||||
isVolatile, MinAlign(Alignment, IncrementSize));
|
isVolatile, MinAlign(Alignment, IncrementSize));
|
||||||
|
@ -1076,7 +1076,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
|
||||||
// Increment the pointer to the other half.
|
// Increment the pointer to the other half.
|
||||||
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
|
unsigned IncrementSize = MVT::getSizeInBits(NVT)/8;
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
|
Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
|
||||||
SVOffset+IncrementSize, NEVT,
|
SVOffset+IncrementSize, NEVT,
|
||||||
isVolatile, MinAlign(Alignment, IncrementSize));
|
isVolatile, MinAlign(Alignment, IncrementSize));
|
||||||
|
@ -1110,7 +1110,7 @@ SDOperand DAGTypeLegalizer::ExpandOperand_STORE(StoreSDNode *N, unsigned OpNo) {
|
||||||
|
|
||||||
// Increment the pointer to the other half.
|
// Increment the pointer to the other half.
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
// Store the lowest ExcessBits bits in the second half.
|
// Store the lowest ExcessBits bits in the second half.
|
||||||
Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
|
Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
|
||||||
SVOffset+IncrementSize,
|
SVOffset+IncrementSize,
|
||||||
|
|
|
@ -144,8 +144,11 @@ SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) {
|
||||||
|
|
||||||
SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
|
SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
|
||||||
// NOTE: Assumes input is legal.
|
// NOTE: Assumes input is legal.
|
||||||
|
if (N->getConstantOperandVal(1) == 0)
|
||||||
return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
|
return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
|
||||||
N->getOperand(0), DAG.getValueType(N->getValueType(0)));
|
N->getOperand(0), DAG.getValueType(N->getValueType(0)));
|
||||||
|
// If the precision discard isn't needed, just return the operand unrounded.
|
||||||
|
return N->getOperand(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
|
SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
|
||||||
|
@ -353,7 +356,8 @@ SDOperand DAGTypeLegalizer::PromoteOperand_FP_EXTEND(SDNode *N) {
|
||||||
|
|
||||||
SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
|
SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
|
||||||
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
SDOperand Op = GetPromotedOp(N->getOperand(0));
|
||||||
return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op);
|
return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
|
||||||
|
DAG.getIntPtrConstant(0));
|
||||||
}
|
}
|
||||||
|
|
||||||
SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
|
SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
|
||||||
|
|
|
@ -139,7 +139,7 @@ void DAGTypeLegalizer::SplitRes_LOAD(LoadSDNode *LD,
|
||||||
Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
|
Lo = DAG.getLoad(LoVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
|
||||||
unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8;
|
unsigned IncrementSize = MVT::getSizeInBits(LoVT)/8;
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
SVOffset += IncrementSize;
|
SVOffset += IncrementSize;
|
||||||
Alignment = MinAlign(Alignment, IncrementSize);
|
Alignment = MinAlign(Alignment, IncrementSize);
|
||||||
Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
|
Hi = DAG.getLoad(HiVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
|
||||||
|
@ -380,7 +380,7 @@ SDOperand DAGTypeLegalizer::SplitOp_STORE(StoreSDNode *N, unsigned OpNo) {
|
||||||
|
|
||||||
// Increment the pointer to the other half.
|
// Increment the pointer to the other half.
|
||||||
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
||||||
getIntPtrConstant(IncrementSize));
|
DAG.getIntPtrConstant(IncrementSize));
|
||||||
|
|
||||||
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
||||||
isVol, MinAlign(Alignment, IncrementSize));
|
isVol, MinAlign(Alignment, IncrementSize));
|
||||||
|
|
|
@ -710,6 +710,11 @@ SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT, bool isT) {
|
||||||
return Result;
|
return Result;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
SDOperand SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) {
|
||||||
|
return getConstant(Val, TLI.getPointerTy(), isTarget);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT,
|
SDOperand SelectionDAG::getConstantFP(const APFloat& V, MVT::ValueType VT,
|
||||||
bool isTarget) {
|
bool isTarget) {
|
||||||
assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!");
|
assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!");
|
||||||
|
@ -1704,7 +1709,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
|
||||||
// Constant fold unary operations with a floating point constant operand.
|
// Constant fold unary operations with a floating point constant operand.
|
||||||
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) {
|
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) {
|
||||||
APFloat V = C->getValueAPF(); // make copy
|
APFloat V = C->getValueAPF(); // make copy
|
||||||
if (VT!=MVT::ppcf128 && Operand.getValueType()!=MVT::ppcf128) {
|
if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
|
||||||
switch (Opcode) {
|
switch (Opcode) {
|
||||||
case ISD::FNEG:
|
case ISD::FNEG:
|
||||||
V.changeSign();
|
V.changeSign();
|
||||||
|
@ -1749,7 +1754,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
|
||||||
switch (Opcode) {
|
switch (Opcode) {
|
||||||
case ISD::TokenFactor:
|
case ISD::TokenFactor:
|
||||||
return Operand; // Factor of one node? No factor.
|
return Operand; // Factor of one node? No factor.
|
||||||
case ISD::FP_ROUND:
|
case ISD::FP_ROUND: assert(0 && "Invalid method to make FP_ROUND node");
|
||||||
case ISD::FP_EXTEND:
|
case ISD::FP_EXTEND:
|
||||||
assert(MVT::isFloatingPoint(VT) &&
|
assert(MVT::isFloatingPoint(VT) &&
|
||||||
MVT::isFloatingPoint(Operand.getValueType()) && "Invalid FP cast!");
|
MVT::isFloatingPoint(Operand.getValueType()) && "Invalid FP cast!");
|
||||||
|
@ -1909,6 +1914,13 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
|
||||||
"Not rounding down!");
|
"Not rounding down!");
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
case ISD::FP_ROUND:
|
||||||
|
assert(MVT::isFloatingPoint(VT) &&
|
||||||
|
MVT::isFloatingPoint(N1.getValueType()) &&
|
||||||
|
MVT::getSizeInBits(VT) <= MVT::getSizeInBits(N1.getValueType()) &&
|
||||||
|
isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
|
||||||
|
if (N1.getValueType() == VT) return N1; // noop conversion.
|
||||||
|
break;
|
||||||
case ISD::AssertSext:
|
case ISD::AssertSext:
|
||||||
case ISD::AssertZext:
|
case ISD::AssertZext:
|
||||||
case ISD::SIGN_EXTEND_INREG: {
|
case ISD::SIGN_EXTEND_INREG: {
|
||||||
|
|
|
@ -483,10 +483,6 @@ public:
|
||||||
const Value *SV, SDOperand Root,
|
const Value *SV, SDOperand Root,
|
||||||
bool isVolatile, unsigned Alignment);
|
bool isVolatile, unsigned Alignment);
|
||||||
|
|
||||||
SDOperand getIntPtrConstant(uint64_t Val) {
|
|
||||||
return DAG.getConstant(Val, TLI.getPointerTy());
|
|
||||||
}
|
|
||||||
|
|
||||||
SDOperand getValue(const Value *V);
|
SDOperand getValue(const Value *V);
|
||||||
|
|
||||||
void setValue(const Value *V, SDOperand NewN) {
|
void setValue(const Value *V, SDOperand NewN) {
|
||||||
|
@ -677,12 +673,10 @@ static SDOperand getCopyFromParts(SelectionDAG &DAG,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (MVT::isFloatingPoint(PartVT) &&
|
if (MVT::isFloatingPoint(PartVT) && MVT::isFloatingPoint(ValueVT))
|
||||||
MVT::isFloatingPoint(ValueVT))
|
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val, DAG.getIntPtrConstant(0));
|
||||||
return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
|
|
||||||
|
|
||||||
if (MVT::getSizeInBits(PartVT) ==
|
if (MVT::getSizeInBits(PartVT) == MVT::getSizeInBits(ValueVT))
|
||||||
MVT::getSizeInBits(ValueVT))
|
|
||||||
return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
|
return DAG.getNode(ISD::BIT_CONVERT, ValueVT, Val);
|
||||||
|
|
||||||
assert(0 && "Unknown mismatch!");
|
assert(0 && "Unknown mismatch!");
|
||||||
|
@ -2163,7 +2157,7 @@ void SelectionDAGLowering::visitFPTrunc(User &I) {
|
||||||
// FPTrunc is never a no-op cast, no need to check
|
// FPTrunc is never a no-op cast, no need to check
|
||||||
SDOperand N = getValue(I.getOperand(0));
|
SDOperand N = getValue(I.getOperand(0));
|
||||||
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
MVT::ValueType DestVT = TLI.getValueType(I.getType());
|
||||||
setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
|
setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N, DAG.getIntPtrConstant(0)));
|
||||||
}
|
}
|
||||||
|
|
||||||
void SelectionDAGLowering::visitFPExt(User &I){
|
void SelectionDAGLowering::visitFPExt(User &I){
|
||||||
|
@ -2284,7 +2278,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
|
||||||
// N = N + Offset
|
// N = N + Offset
|
||||||
uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
|
uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
|
||||||
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
|
||||||
getIntPtrConstant(Offset));
|
DAG.getIntPtrConstant(Offset));
|
||||||
}
|
}
|
||||||
Ty = StTy->getElementType(Field);
|
Ty = StTy->getElementType(Field);
|
||||||
} else {
|
} else {
|
||||||
|
@ -2295,7 +2289,8 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
|
||||||
if (CI->getZExtValue() == 0) continue;
|
if (CI->getZExtValue() == 0) continue;
|
||||||
uint64_t Offs =
|
uint64_t Offs =
|
||||||
TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
|
TD->getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
|
||||||
N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
|
||||||
|
DAG.getIntPtrConstant(Offs));
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2320,7 +2315,7 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) {
|
||||||
continue;
|
continue;
|
||||||
}
|
}
|
||||||
|
|
||||||
SDOperand Scale = getIntPtrConstant(ElementSize);
|
SDOperand Scale = DAG.getIntPtrConstant(ElementSize);
|
||||||
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
|
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
|
||||||
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
|
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
|
||||||
}
|
}
|
||||||
|
@ -2348,7 +2343,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
|
||||||
AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
|
AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
|
||||||
|
|
||||||
AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
|
AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
|
||||||
getIntPtrConstant(TySize));
|
DAG.getIntPtrConstant(TySize));
|
||||||
|
|
||||||
// Handle alignment. If the requested alignment is less than or equal to
|
// Handle alignment. If the requested alignment is less than or equal to
|
||||||
// the stack alignment, ignore it. If the size is greater than or equal to
|
// the stack alignment, ignore it. If the size is greater than or equal to
|
||||||
|
@ -2361,12 +2356,12 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
|
||||||
// Round the size of the allocation up to the stack alignment size
|
// Round the size of the allocation up to the stack alignment size
|
||||||
// by add SA-1 to the size.
|
// by add SA-1 to the size.
|
||||||
AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
|
AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
|
||||||
getIntPtrConstant(StackAlign-1));
|
DAG.getIntPtrConstant(StackAlign-1));
|
||||||
// Mask out the low bits for alignment purposes.
|
// Mask out the low bits for alignment purposes.
|
||||||
AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
|
AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
|
||||||
getIntPtrConstant(~(uint64_t)(StackAlign-1)));
|
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
|
||||||
|
|
||||||
SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
|
SDOperand Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
|
||||||
const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
|
const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
|
||||||
MVT::Other);
|
MVT::Other);
|
||||||
SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
|
SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
|
||||||
|
@ -3815,7 +3810,7 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) {
|
||||||
// Scale the source by the type size.
|
// Scale the source by the type size.
|
||||||
uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
|
uint64_t ElementSize = TD->getABITypeSize(I.getType()->getElementType());
|
||||||
Src = DAG.getNode(ISD::MUL, Src.getValueType(),
|
Src = DAG.getNode(ISD::MUL, Src.getValueType(),
|
||||||
Src, getIntPtrConstant(ElementSize));
|
Src, DAG.getIntPtrConstant(ElementSize));
|
||||||
|
|
||||||
TargetLowering::ArgListTy Args;
|
TargetLowering::ArgListTy Args;
|
||||||
TargetLowering::ArgListEntry Entry;
|
TargetLowering::ArgListEntry Entry;
|
||||||
|
@ -3994,7 +3989,7 @@ TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
|
||||||
Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
|
Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
|
||||||
} else {
|
} else {
|
||||||
assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
|
assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
|
||||||
Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
|
Op = DAG.getNode(ISD::FP_ROUND, VT, Op, DAG.getIntPtrConstant(1));
|
||||||
}
|
}
|
||||||
Ops.push_back(Op);
|
Ops.push_back(Op);
|
||||||
break;
|
break;
|
||||||
|
|
|
@ -193,7 +193,8 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
|
||||||
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
|
argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
|
||||||
MVT::f64);
|
MVT::f64);
|
||||||
if (I->getType() == Type::FloatTy)
|
if (I->getType() == Type::FloatTy)
|
||||||
argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
|
argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
|
||||||
|
DAG.getIntPtrConstant(0));
|
||||||
break;
|
break;
|
||||||
case MVT::i1: // NOTE: as far as C abi stuff goes,
|
case MVT::i1: // NOTE: as far as C abi stuff goes,
|
||||||
// bools are just boring old ints
|
// bools are just boring old ints
|
||||||
|
|
|
@ -2171,7 +2171,7 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
||||||
SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
|
SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
|
||||||
SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
|
SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
|
||||||
if (Op.getValueType() == MVT::f32)
|
if (Op.getValueType() == MVT::f32)
|
||||||
FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
|
FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
|
||||||
return FP;
|
return FP;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2199,7 +2199,7 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
|
||||||
// FCFID it and return it.
|
// FCFID it and return it.
|
||||||
SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
|
SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
|
||||||
if (Op.getValueType() == MVT::f32)
|
if (Op.getValueType() == MVT::f32)
|
||||||
FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
|
FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
|
||||||
return FP;
|
return FP;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -3170,7 +3170,8 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
|
||||||
Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
|
Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
|
||||||
DCI.AddToWorklist(Val.Val);
|
DCI.AddToWorklist(Val.Val);
|
||||||
if (N->getValueType(0) == MVT::f32) {
|
if (N->getValueType(0) == MVT::f32) {
|
||||||
Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
|
Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
|
||||||
|
DAG.getIntPtrConstant(0));
|
||||||
DCI.AddToWorklist(Val.Val);
|
DCI.AddToWorklist(Val.Val);
|
||||||
}
|
}
|
||||||
return Val;
|
return Val;
|
||||||
|
|
|
@ -1182,8 +1182,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
|
||||||
SmallVector<SDOperand, 8> MemOps;
|
SmallVector<SDOperand, 8> MemOps;
|
||||||
SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
|
SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
|
||||||
SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
|
SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
|
||||||
DAG.getConstant(VarArgsGPOffset,
|
DAG.getIntPtrConstant(VarArgsGPOffset));
|
||||||
getPointerTy()));
|
|
||||||
for (; NumIntRegs != 6; ++NumIntRegs) {
|
for (; NumIntRegs != 6; ++NumIntRegs) {
|
||||||
unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
|
unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
|
||||||
X86::GR64RegisterClass);
|
X86::GR64RegisterClass);
|
||||||
|
@ -1191,12 +1190,12 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
|
||||||
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
||||||
MemOps.push_back(Store);
|
MemOps.push_back(Store);
|
||||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
||||||
DAG.getConstant(8, getPointerTy()));
|
DAG.getIntPtrConstant(8));
|
||||||
}
|
}
|
||||||
|
|
||||||
// Now store the XMM (fp + vector) parameter registers.
|
// Now store the XMM (fp + vector) parameter registers.
|
||||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
|
||||||
DAG.getConstant(VarArgsFPOffset, getPointerTy()));
|
DAG.getIntPtrConstant(VarArgsFPOffset));
|
||||||
for (; NumXMMRegs != 8; ++NumXMMRegs) {
|
for (; NumXMMRegs != 8; ++NumXMMRegs) {
|
||||||
unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
|
unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
|
||||||
X86::VR128RegisterClass);
|
X86::VR128RegisterClass);
|
||||||
|
@ -1204,7 +1203,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
|
||||||
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
||||||
MemOps.push_back(Store);
|
MemOps.push_back(Store);
|
||||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
||||||
DAG.getConstant(16, getPointerTy()));
|
DAG.getIntPtrConstant(16));
|
||||||
}
|
}
|
||||||
if (!MemOps.empty())
|
if (!MemOps.empty())
|
||||||
Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
||||||
|
@ -1253,7 +1252,7 @@ X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
|
||||||
const CCValAssign &VA,
|
const CCValAssign &VA,
|
||||||
SDOperand Chain,
|
SDOperand Chain,
|
||||||
SDOperand Arg) {
|
SDOperand Arg) {
|
||||||
SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
|
SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
|
||||||
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
|
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
|
||||||
SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
|
SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
|
||||||
unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
|
unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
|
||||||
|
@ -1306,7 +1305,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
|
||||||
MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
|
MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
|
||||||
}
|
}
|
||||||
|
|
||||||
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
|
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
|
||||||
|
|
||||||
SDOperand RetAddrFrIdx, NewRetAddrFrIdx;
|
SDOperand RetAddrFrIdx, NewRetAddrFrIdx;
|
||||||
if (IsTailCall) {
|
if (IsTailCall) {
|
||||||
|
@ -1440,7 +1439,7 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
|
||||||
// needs to be done because if we would lower the arguments directly
|
// needs to be done because if we would lower the arguments directly
|
||||||
// to their real stack slot we might end up overwriting each other.
|
// to their real stack slot we might end up overwriting each other.
|
||||||
// Get source stack slot.
|
// Get source stack slot.
|
||||||
Source = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
|
Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
|
||||||
if (StackPtr.Val == 0)
|
if (StackPtr.Val == 0)
|
||||||
StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
|
StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
|
||||||
Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
|
Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
|
||||||
|
@ -1501,8 +1500,8 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
|
||||||
|
|
||||||
if (IsTailCall) {
|
if (IsTailCall) {
|
||||||
Ops.push_back(Chain);
|
Ops.push_back(Chain);
|
||||||
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
|
Ops.push_back(DAG.getIntPtrConstant(NumBytes));
|
||||||
Ops.push_back(DAG.getConstant(0, getPointerTy()));
|
Ops.push_back(DAG.getIntPtrConstant(0));
|
||||||
if (InFlag.Val)
|
if (InFlag.Val)
|
||||||
Ops.push_back(InFlag);
|
Ops.push_back(InFlag);
|
||||||
Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
|
Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
|
||||||
|
@ -1560,9 +1559,8 @@ SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
|
||||||
|
|
||||||
// Returns a flag for retval copy to use.
|
// Returns a flag for retval copy to use.
|
||||||
Chain = DAG.getCALLSEQ_END(Chain,
|
Chain = DAG.getCALLSEQ_END(Chain,
|
||||||
DAG.getConstant(NumBytes, getPointerTy()),
|
DAG.getIntPtrConstant(NumBytes),
|
||||||
DAG.getConstant(NumBytesForCalleeToPush,
|
DAG.getIntPtrConstant(NumBytesForCalleeToPush),
|
||||||
getPointerTy()),
|
|
||||||
InFlag);
|
InFlag);
|
||||||
InFlag = Chain.getValue(1);
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
|
@ -2732,7 +2730,7 @@ static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
|
||||||
|
|
||||||
if (ThisElt.Val)
|
if (ThisElt.Val)
|
||||||
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
|
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
|
||||||
DAG.getConstant(i/2, TLI.getPointerTy()));
|
DAG.getIntPtrConstant(i/2));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2760,7 +2758,7 @@ static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
|
||||||
First = false;
|
First = false;
|
||||||
}
|
}
|
||||||
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
|
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
|
||||||
DAG.getConstant(i, TLI.getPointerTy()));
|
DAG.getIntPtrConstant(i));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -3569,7 +3567,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||||
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
|
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
|
||||||
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
|
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
|
||||||
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
|
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
|
||||||
DAG.getConstant(0, getPointerTy()));
|
DAG.getIntPtrConstant(0));
|
||||||
} else if (MVT::getSizeInBits(VT) == 64) {
|
} else if (MVT::getSizeInBits(VT) == 64) {
|
||||||
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
|
||||||
if (Idx == 0)
|
if (Idx == 0)
|
||||||
|
@ -3589,7 +3587,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||||
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
|
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
|
||||||
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
|
Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
|
||||||
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
|
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
|
||||||
DAG.getConstant(0, getPointerTy()));
|
DAG.getIntPtrConstant(0));
|
||||||
}
|
}
|
||||||
|
|
||||||
return SDOperand();
|
return SDOperand();
|
||||||
|
@ -3612,7 +3610,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
|
||||||
if (N1.getValueType() != MVT::i32)
|
if (N1.getValueType() != MVT::i32)
|
||||||
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
|
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
|
||||||
if (N2.getValueType() != MVT::i32)
|
if (N2.getValueType() != MVT::i32)
|
||||||
N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy());
|
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
|
||||||
return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
|
return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
|
||||||
}
|
}
|
||||||
return SDOperand();
|
return SDOperand();
|
||||||
|
@ -4050,7 +4048,7 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
|
||||||
}
|
}
|
||||||
// And if it is bigger, shrink it first.
|
// And if it is bigger, shrink it first.
|
||||||
if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
|
if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
|
||||||
Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1);
|
Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
|
||||||
SrcVT = VT;
|
SrcVT = VT;
|
||||||
SrcTy = MVT::getTypeForValueType(SrcVT);
|
SrcTy = MVT::getTypeForValueType(SrcVT);
|
||||||
}
|
}
|
||||||
|
@ -4083,7 +4081,7 @@ SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
|
||||||
DAG.getConstant(32, MVT::i32));
|
DAG.getConstant(32, MVT::i32));
|
||||||
SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
|
SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
|
||||||
SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
|
SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
|
||||||
DAG.getConstant(0, getPointerTy()));
|
DAG.getIntPtrConstant(0));
|
||||||
}
|
}
|
||||||
|
|
||||||
// Clear first operand sign bit.
|
// Clear first operand sign bit.
|
||||||
|
@ -4247,7 +4245,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
|
||||||
SDOperand Flag;
|
SDOperand Flag;
|
||||||
|
|
||||||
MVT::ValueType IntPtr = getPointerTy();
|
MVT::ValueType IntPtr = getPointerTy();
|
||||||
MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
|
MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
|
||||||
|
|
||||||
Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
|
Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
|
||||||
Flag = Chain.getValue(1);
|
Flag = Chain.getValue(1);
|
||||||
|
@ -4338,7 +4336,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
|
||||||
if (AVT > MVT::i8) {
|
if (AVT > MVT::i8) {
|
||||||
if (I) {
|
if (I) {
|
||||||
unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
|
unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
|
||||||
Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
|
Count = DAG.getIntPtrConstant(I->getValue() / UBytes);
|
||||||
BytesLeft = I->getValue() % UBytes;
|
BytesLeft = I->getValue() % UBytes;
|
||||||
} else {
|
} else {
|
||||||
assert(AVT >= MVT::i32 &&
|
assert(AVT >= MVT::i32 &&
|
||||||
|
@ -4450,7 +4448,7 @@ SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
|
unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
|
||||||
SDOperand Count = DAG.getConstant(Size / UBytes, getPointerTy());
|
SDOperand Count = DAG.getIntPtrConstant(Size / UBytes);
|
||||||
BytesLeft = Size % UBytes;
|
BytesLeft = Size % UBytes;
|
||||||
|
|
||||||
SDOperand InFlag(0, 0);
|
SDOperand InFlag(0, 0);
|
||||||
|
@ -4579,24 +4577,21 @@ SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
|
||||||
MemOps.push_back(Store);
|
MemOps.push_back(Store);
|
||||||
|
|
||||||
// Store fp_offset
|
// Store fp_offset
|
||||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
|
||||||
DAG.getConstant(4, getPointerTy()));
|
|
||||||
Store = DAG.getStore(Op.getOperand(0),
|
Store = DAG.getStore(Op.getOperand(0),
|
||||||
DAG.getConstant(VarArgsFPOffset, MVT::i32),
|
DAG.getConstant(VarArgsFPOffset, MVT::i32),
|
||||||
FIN, SV->getValue(), SV->getOffset());
|
FIN, SV->getValue(), SV->getOffset());
|
||||||
MemOps.push_back(Store);
|
MemOps.push_back(Store);
|
||||||
|
|
||||||
// Store ptr to overflow_arg_area
|
// Store ptr to overflow_arg_area
|
||||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
|
||||||
DAG.getConstant(4, getPointerTy()));
|
|
||||||
SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
|
SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
|
||||||
Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
|
Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
|
||||||
SV->getOffset());
|
SV->getOffset());
|
||||||
MemOps.push_back(Store);
|
MemOps.push_back(Store);
|
||||||
|
|
||||||
// Store ptr to reg_save_area.
|
// Store ptr to reg_save_area.
|
||||||
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
|
||||||
DAG.getConstant(8, getPointerTy()));
|
|
||||||
SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
|
SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
|
||||||
Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
|
Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
|
||||||
SV->getOffset());
|
SV->getOffset());
|
||||||
|
@ -4624,9 +4619,9 @@ SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
|
||||||
if (i == 2)
|
if (i == 2)
|
||||||
break;
|
break;
|
||||||
SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
|
SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
|
||||||
DAG.getConstant(8, getPointerTy()));
|
DAG.getIntPtrConstant(8));
|
||||||
DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
|
DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
|
||||||
DAG.getConstant(8, getPointerTy()));
|
DAG.getIntPtrConstant(8));
|
||||||
}
|
}
|
||||||
return Chain;
|
return Chain;
|
||||||
}
|
}
|
||||||
|
@ -4757,7 +4752,7 @@ SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
|
||||||
|
|
||||||
SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
|
SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
|
||||||
return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
|
return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
|
||||||
DAG.getConstant(4, getPointerTy()));
|
DAG.getIntPtrConstant(4));
|
||||||
}
|
}
|
||||||
|
|
||||||
SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
|
SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
|
||||||
|
@ -4766,7 +4761,7 @@ SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
|
||||||
if (Subtarget->is64Bit())
|
if (Subtarget->is64Bit())
|
||||||
return SDOperand();
|
return SDOperand();
|
||||||
|
|
||||||
return DAG.getConstant(8, getPointerTy());
|
return DAG.getIntPtrConstant(8);
|
||||||
}
|
}
|
||||||
|
|
||||||
SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
|
SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
|
||||||
|
@ -4783,7 +4778,7 @@ SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
|
||||||
getPointerTy());
|
getPointerTy());
|
||||||
|
|
||||||
SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
|
SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
|
||||||
DAG.getConstant(-4UL, getPointerTy()));
|
DAG.getIntPtrConstant(-4UL));
|
||||||
StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
|
StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
|
||||||
Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
|
Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
|
||||||
Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
|
Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
|
||||||
|
|
Loading…
Reference in New Issue