don't bother making x&-1 only to simplify it in dag combine. This commonly occurs expanding i64 ops.

llvm-svn: 46383
2008-01-26 01:05:42 +00:00 · 2008-01-26 01:05:42 +00:00 · 720d8999c7
parent 2df73ea849
commit 720d8999c7
1 changed files with 2 additions and 0 deletions
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@ -1877,6 +1877,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
    // worth handling here.
    if (N2C && N2C->getValue() == 0)
      return N2;
+    if (N2C && N2C->isAllOnesValue())  // X & -1 -> X
+      return N1;
    break;
  case ISD::OR:
  case ISD::XOR: