Use intrinsics for Neon vmull operations. Radar 9208957.
llvm-svn: 128590
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@ -22,13 +22,11 @@ def OP_SUB : Op;
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def OP_SUBL : Op;
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def OP_SUBL : Op;
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def OP_SUBW : Op;
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def OP_SUBW : Op;
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def OP_MUL : Op;
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def OP_MUL : Op;
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def OP_MULL : Op;
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def OP_MLA : Op;
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def OP_MLA : Op;
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def OP_MLAL : Op;
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def OP_MLAL : Op;
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def OP_MLS : Op;
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def OP_MLS : Op;
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def OP_MLSL : Op;
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def OP_MLSL : Op;
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def OP_MUL_N : Op;
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def OP_MUL_N : Op;
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def OP_MULL_N: Op;
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def OP_MLA_N : Op;
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def OP_MLA_N : Op;
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def OP_MLS_N : Op;
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def OP_MLS_N : Op;
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def OP_MLAL_N : Op;
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def OP_MLAL_N : Op;
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@ -144,8 +142,7 @@ def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">;
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def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
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def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
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def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">;
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def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">;
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def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
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def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
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def VMULL : Inst<"vmull", "wdd", "csiUcUsUi", OP_MULL>;
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def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">;
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def VMULLP : SInst<"vmull", "wdd", "Pc">;
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def VQDMULL : SInst<"vqdmull", "wdd", "si">;
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def VQDMULL : SInst<"vqdmull", "wdd", "si">;
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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@ -331,7 +328,7 @@ def VMLSL_LANE : Inst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>;
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def VQDMLSL_LANE : Inst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>;
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def VQDMLSL_LANE : Inst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>;
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def VMUL_N : Inst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
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def VMUL_N : Inst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>;
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def VMUL_LANE : Inst<"vmul_lane", "ddgi", "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
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def VMUL_LANE : Inst<"vmul_lane", "ddgi", "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>;
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def VMULL_N : Inst<"vmull_n", "wda", "siUsUi", OP_MULL_N>;
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def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">;
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def VMULL_LANE : Inst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>;
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def VMULL_LANE : Inst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>;
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def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">;
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def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">;
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def VQDMULL_LANE : Inst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>;
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def VQDMULL_LANE : Inst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>;
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@ -1464,9 +1464,9 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vmulp, &Ty, 1),
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vmulp, &Ty, 1),
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Ops, "vmul");
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Ops, "vmul");
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case ARM::BI__builtin_neon_vmull_v:
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case ARM::BI__builtin_neon_vmull_v:
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assert(poly && "vmull builtin only supported for polynomial types");
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Int = usgn ? Intrinsic::arm_neon_vmullu : Intrinsic::arm_neon_vmulls;
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return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vmullp, &Ty, 1),
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Int = poly ? Intrinsic::arm_neon_vmullp : Int;
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Ops, "vmull");
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return EmitNeonCall(CGM.getIntrinsic(Int, &Ty, 1), Ops, "vmull");
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case ARM::BI__builtin_neon_vpadal_v:
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case ARM::BI__builtin_neon_vpadal_v:
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case ARM::BI__builtin_neon_vpadalq_v: {
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case ARM::BI__builtin_neon_vpadalq_v: {
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Int = usgn ? Intrinsic::arm_neon_vpadalu : Intrinsic::arm_neon_vpadals;
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Int = usgn ? Intrinsic::arm_neon_vpadalu : Intrinsic::arm_neon_vpadals;
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