Model prefetches and barriers as loads.
It's not yet clear if these instructions need a more careful model. llvm-svn: 177599
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@ -3487,7 +3487,7 @@ def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
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//===----------------------------------------------------------------------===//
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// Prefetch intrinsic.
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let Predicates = [HasSSE1] in {
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let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
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def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
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"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
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IIC_SSE_PREFETCH>, TB;
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@ -3502,6 +3502,8 @@ def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
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IIC_SSE_PREFETCH>, TB;
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}
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// FIXME: How should these memory instructions be modeled?
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let SchedRW = [WriteLoad] in {
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// Flush cache
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def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
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"clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
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@ -3521,6 +3523,7 @@ def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
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def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
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"mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
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TB, Requires<[HasSSE2]>;
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} // SchedRW
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def : Pat<(X86SFence), (SFENCE)>;
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def : Pat<(X86LFence), (LFENCE)>;
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