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SDAGBuilder: Remove register sets that were never read and prune dead code surrounding it. 

llvm-svn: 151364
This commit is contained in:
Benjamin Kramer 2012-02-24 14:01:17 +00:00
parent b59291a8e6
commit 6fe3e3d335
1 changed files with 3 additions and 63 deletions
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66
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -5677,22 +5677,6 @@ public:
: TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
}
/// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
/// busy in OutputRegs/InputRegs.
void MarkAllocatedRegs(bool isOutReg, bool isInReg,
std::set<unsigned> &OutputRegs,
std::set<unsigned> &InputRegs,
const TargetRegisterInfo &TRI) const {
if (isOutReg) {
for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
}
if (isInReg) {
for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
}
}
/// getCallOperandValEVT - Return the EVT of the Value* that this operand
/// corresponds to. If there is no Value* for this operand, it returns
/// MVT::Other.
@ -5740,18 +5724,6 @@ public:
return TLI.getValueType(OpTy, true);
}
private:
/// MarkRegAndAliases - Mark the specified register and all aliases in the
/// specified set.
static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
const TargetRegisterInfo &TRI) {
assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
Regs.insert(Reg);
if (const unsigned *Aliases = TRI.getAliasSet(Reg))
for (; *Aliases; ++Aliases)
Regs.insert(*Aliases);
}
};
typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
@ -5765,39 +5737,13 @@ typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
/// allocation. This produces generally horrible, but correct, code.
///
/// OpInfo describes the operand.
/// Input and OutputRegs are the set of already allocated physical registers.
///
static void GetRegistersForValue(SelectionDAG &DAG,
const TargetLowering &TLI,
DebugLoc DL,
SDISelAsmOperandInfo &OpInfo,
std::set<unsigned> &OutputRegs,
std::set<unsigned> &InputRegs) {
SDISelAsmOperandInfo &OpInfo) {
LLVMContext &Context = *DAG.getContext();
// Compute whether this value requires an input register, an output register,
// or both.
bool isOutReg = false;
bool isInReg = false;
switch (OpInfo.Type) {
case InlineAsm::isOutput:
isOutReg = true;
// If there is an input constraint that matches this, we need to reserve
// the input register so no other inputs allocate to it.
isInReg = OpInfo.hasMatchingInput();
break;
case InlineAsm::isInput:
isInReg = true;
isOutReg = false;
break;
case InlineAsm::isClobber:
isOutReg = true;
isInReg = true;
break;
}
MachineFunction &MF = DAG.getMachineFunction();
SmallVector<unsigned, 4> Regs;
@ -5871,8 +5817,6 @@ static void GetRegistersForValue(SelectionDAG &DAG,
}
OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
return;
}
@ -5903,8 +5847,6 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
/// ConstraintOperands - Information about all of the constraints.
SDISelAsmOperandInfoVector ConstraintOperands;
std::set<unsigned> OutputRegs, InputRegs;
TargetLowering::AsmOperandInfoVector
TargetConstraints = TLI.ParseConstraints(CS);
@ -6066,8 +6008,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// If this constraint is for a specific register, allocate it before
// anything else.
if (OpInfo.ConstraintType == TargetLowering::C_Register)
GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
InputRegs);
GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
}
// Second pass - Loop over all of the operands, assigning virtual or physregs
@ -6078,8 +6019,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// C_Register operands have already been allocated, Other/Memory don't need
// to be.
if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
InputRegs);
GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
}
// AsmNodeOperands - The operands for the ISD::INLINEASM node.