When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add the new node into the work list because there is a potential for further optimizations.
llvm-svn: 152784
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@ -7422,6 +7422,8 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
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// will be type-legalized to complex code sequences.
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// We perform this optimization only before the operation legalizer because we
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// may introduce illegal operations.
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// Create a new simpler BUILD_VECTOR sequence which other optimizations can
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// turn into a single shuffle instruction.
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if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) &&
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ValidTypes) {
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bool isLE = TLI.isLittleEndian();
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@ -7462,6 +7464,8 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
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SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
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VecVT, &Ops[0], Ops.size());
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// The new BUILD_VECTOR node has the potential to be further optimized.
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AddToWorkList(BV.getNode());
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// Bitcast to the desired type.
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return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
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}
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@ -0,0 +1,10 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: build_vector_again
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define <4 x i8> @build_vector_again(<16 x i8> %in) nounwind readnone {
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entry:
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%out = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK: shufb
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ret <4 x i8> %out
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; CHECK: ret
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}
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