Add PPC 440 scheduler and some associated tests

llvm-svn: 142170

llvm/lib/Target/PowerPC/PPC.td

@@ -23,6 +23,7 @@ include "llvm/Target/Target.td"
 // CPU Directives                                                             //
 //===----------------------------------------------------------------------===//
 
+def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
@@ -46,6 +47,8 @@ def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
                                         "Enable the fsqrt instruction">;
 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
                                         "Enable the stfiwx instruction">;
+def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
+                                        "Enable Book E instructions">;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
@@ -60,6 +63,8 @@ include "PPCInstrInfo.td"
 //
 
 def : Processor<"generic", G3Itineraries, [Directive32]>;
+def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>;
+def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>;
 def : Processor<"601", G3Itineraries, [Directive601]>;
 def : Processor<"602", G3Itineraries, [Directive602]>;
 def : Processor<"603", G3Itineraries, [Directive603]>;

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

@@ -374,6 +374,12 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
     OutStreamer.EmitInstruction(TmpInst);
     return;
+  case PPC::SYNC:
+    // In Book E sync is called msync, handle this special case here...
+    if (Subtarget.isBookE()) {
+      OutStreamer.EmitRawText(StringRef("\tmsync"));
+      return;
+    }
   }
 
   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
@@ -421,6 +427,7 @@ void PPCDarwinAsmPrinter::EmitStartOfAsmFile(Module &M) {
   static const char *const CPUDirectives[] = {
     "",
     "ppc",
+    "ppc440",
     "ppc601",
     "ppc602",
     "ppc603",

llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp

@@ -21,6 +21,19 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
+//===----------------------------------------------------------------------===//
+// PowerPC 440 Hazard Recognizer
+void PPCHazardRecognizer440::EmitInstruction(SUnit *SU) {
+  const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
+  if (!MCID) {
+    // This is a PPC pseudo-instruction.
+    // FIXME: Should something else be done?
+    return;
+  }
+
+  ScoreboardHazardRecognizer::EmitInstruction(SU);
+}
+
 //===----------------------------------------------------------------------===//
 // PowerPC 970 Hazard Recognizer
 //

llvm/lib/Target/PowerPC/PPCHazardRecognizers.h

@@ -15,11 +15,24 @@
 #define PPCHAZRECS_H
 
 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "PPCInstrInfo.h"
 
 namespace llvm {
 
+/// PPCHazardRecognizer440 - This class implements a scoreboard-based
+/// hazard recognizer for the PPC 440 and friends.
+class PPCHazardRecognizer440 : public ScoreboardHazardRecognizer {
+  const ScheduleDAG *DAG;
+public:
+  PPCHazardRecognizer440(const InstrItineraryData *ItinData,
+                         const ScheduleDAG *DAG_) :
+    ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
+
+  virtual void EmitInstruction(SUnit *SU);
+};
+
 /// PPCHazardRecognizer970 - This class defines a finite state automata that
 /// models the dispatch logic on the PowerPC 970 (aka G5) processor.  This
 /// promotes good dispatch group formation and implements noop insertion to

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -53,7 +53,15 @@ ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
   // now, always return a PPC970 recognizer.
   const TargetInstrInfo *TII = TM->getInstrInfo();
   assert(TII && "No InstrInfo?");
-  return new PPCHazardRecognizer970(*TII);
+
+  unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
+  if (Directive == PPC::DIR_440) {
+    const InstrItineraryData *II = TM->getInstrItineraryData();
+    return new PPCHazardRecognizer440(II, DAG);
+  }
+  else {
+    return new PPCHazardRecognizer970(*TII);
+  }
 }
 
 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,

llvm/lib/Target/PowerPC/PPCInstrInfo.td

@@ -352,7 +352,7 @@ def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
 def FPContractions : Predicate<"!NoExcessFPPrecision">;
 def In32BitMode  : Predicate<"!PPCSubTarget.isPPC64()">;
 def In64BitMode  : Predicate<"PPCSubTarget.isPPC64()">;
-
+def IsBookE  : Predicate<"PPCSubTarget.isBookE()">;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Definitions.

llvm/lib/Target/PowerPC/PPCSchedule.td

@@ -103,6 +103,7 @@ def VecVSR       : InstrItinClass;
 // Processor instruction itineraries.
 
 include "PPCScheduleG3.td"
+include "PPCSchedule440.td"
 include "PPCScheduleG4.td"
 include "PPCScheduleG4Plus.td"
 include "PPCScheduleG5.td"

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

@@ -74,6 +74,7 @@ PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
   , HasAltivec(false)
   , HasFSQRT(false)
   , HasSTFIWX(false)
+  , IsBookE(false)
   , HasLazyResolverStubs(false)
   , IsJITCodeModel(false)
   , TargetTriple(TT) {

llvm/lib/Target/PowerPC/PPCSubtarget.h

@@ -33,6 +33,7 @@ namespace PPC {
   enum {
     DIR_NONE,
     DIR_32,
+    DIR_440, 
     DIR_601, 
     DIR_602, 
     DIR_603, 
@@ -66,6 +67,7 @@ protected:
   bool HasAltivec;
   bool HasFSQRT;
   bool HasSTFIWX;
+  bool IsBookE;
   bool HasLazyResolverStubs;
   bool IsJITCodeModel;
   
@@ -136,6 +138,7 @@ public:
   bool hasSTFIWX() const { return HasSTFIWX; }
   bool hasAltivec() const { return HasAltivec; }
   bool isGigaProcessor() const { return IsGigaProcessor; }
+  bool isBookE() const { return IsBookE; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }