[x86] Teach the new vector shuffle lowering to use the AVX VPERMILPS
instruction for single-vector floating point shuffles. This in turn allows the shuffles to fold a load into the instruction which is one of the common regressions hit with the new shuffle lowering. llvm-svn: 218190
This commit is contained in:
Chandler Carruth
parent
7d0dc3ef18
commit
6f80abac4e
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@ -7772,11 +7772,19 @@ static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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int NumV2Elements =
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std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
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if (NumV2Elements == 0)
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// Straight shuffle of a single input vector. We pass the input vector to
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// both operands to simulate this with a SHUFPS.
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if (NumV2Elements == 0) {
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if (Subtarget->hasAVX()) {
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// If we have AVX, we can use VPERMILPS which will allow folding a load
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// into the shuffle.
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return DAG.getNode(X86ISD::VPERMILP, DL, MVT::v4f32, V1,
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getV4X86ShuffleImm8ForMask(Mask, DAG));
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}
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// Otherwise, use a straight shuffle of a single input vector. We pass the
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// input vector to both operands to simulate this with a SHUFPS.
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return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
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getV4X86ShuffleImm8ForMask(Mask, DAG));
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}
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// Use dedicated unpack instructions for masks that match their pattern.
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if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
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@ -73,51 +73,93 @@ define <4 x i32> @shuffle_v4i32_2121(<4 x i32> %a, <4 x i32> %b) {
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}
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define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) {
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; ALL-LABEL: @shuffle_v4f32_0001
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; ALL: shufps {{.*}} # xmm0 = xmm0[0,0,0,1]
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; ALL-NEXT: retq
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; SSE-LABEL: @shuffle_v4f32_0001
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,0,0,1]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: @shuffle_v4f32_0001
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; AVX: # BB#0:
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; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,0,0,1]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) {
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; ALL-LABEL: @shuffle_v4f32_0020
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; ALL: shufps {{.*}} # xmm0 = xmm0[0,0,2,0]
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; ALL-NEXT: retq
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; SSE-LABEL: @shuffle_v4f32_0020
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,0,2,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: @shuffle_v4f32_0020
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; AVX: # BB#0:
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; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,0,2,0]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) {
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; ALL-LABEL: @shuffle_v4f32_0300
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; ALL: shufps {{.*}} # xmm0 = xmm0[0,3,0,0]
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; ALL-NEXT: retq
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; SSE-LABEL: @shuffle_v4f32_0300
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[0,3,0,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: @shuffle_v4f32_0300
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; AVX: # BB#0:
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; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[0,3,0,0]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) {
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; ALL-LABEL: @shuffle_v4f32_1000
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; ALL: shufps {{.*}} # xmm0 = xmm0[1,0,0,0]
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; ALL-NEXT: retq
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; SSE-LABEL: @shuffle_v4f32_1000
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[1,0,0,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: @shuffle_v4f32_1000
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; AVX: # BB#0:
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; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[1,0,0,0]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) {
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; ALL-LABEL: @shuffle_v4f32_2200
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; ALL: shufps {{.*}} # xmm0 = xmm0[2,2,0,0]
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; ALL-NEXT: retq
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; SSE-LABEL: @shuffle_v4f32_2200
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[2,2,0,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: @shuffle_v4f32_2200
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; AVX: # BB#0:
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; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[2,2,0,0]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) {
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; ALL-LABEL: @shuffle_v4f32_3330
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; ALL: shufps {{.*}} # xmm0 = xmm0[3,3,3,0]
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; ALL-NEXT: retq
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; SSE-LABEL: @shuffle_v4f32_3330
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,3,3,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: @shuffle_v4f32_3330
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; AVX: # BB#0:
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; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[3,3,3,0]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) {
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; ALL-LABEL: @shuffle_v4f32_3210
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; ALL: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
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; ALL-NEXT: retq
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; SSE-LABEL: @shuffle_v4f32_3210
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; SSE: # BB#0:
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: @shuffle_v4f32_3210
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; AVX: # BB#0:
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; AVX-NEXT: vpermilps {{.*}} # xmm0 = xmm0[3,2,1,0]
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; AVX-NEXT: retq
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%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %shuffle
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}
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@ -805,3 +847,19 @@ define <4 x float> @insert_mem_and_zero_v4f32(float* %ptr) {
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%shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %shuffle
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}
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define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) {
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; SSE-LABEL: @shuffle_mem_v4f32_3210
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; SSE: # BB#0:
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; SSE-NEXT: movaps (%rdi), %xmm0
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; SSE-NEXT: shufps {{.*}} # xmm0 = xmm0[3,2,1,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: @shuffle_mem_v4f32_3210
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; AVX: # BB#0:
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; AVX-NEXT: vpermilps {{.*}} # xmm0 = mem[3,2,1,0]
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; AVX-NEXT: retq
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%a = load <4 x float>* %ptr
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%shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %shuffle
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}
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