[X86] DAGCombine should not assume arbitrary vector types are simple
The X86-specific DAGCombine for stores should not assume vector types are always simple. This fixes PR23476. Differential Revision: http://reviews.llvm.org/D9659 llvm-svn: 237097
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@ -23315,7 +23315,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
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SDValue OldExtract = St->getOperand(1);
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SDValue ExtOp0 = OldExtract.getOperand(0);
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unsigned VecSize = ExtOp0.getValueSizeInBits();
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MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64);
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EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
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SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
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SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
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BitCast, OldExtract.getOperand(1));
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@ -63,3 +63,14 @@ define void @store_i64_from_vector256(<16 x i16> %x, <16 x i16> %y, i64* %i) {
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ret void
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}
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; PR23476
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; Handle extraction from a non-simple / pre-legalization type.
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define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) {
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; X32-LABEL: PR23476:
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; X32: movsd {{.*#+}} xmm0 = mem[0],zero
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; X32-NEXT: movsd %xmm0, (%eax)
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%ext = extractelement <5 x i64> %in, i32 %index
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store i64 %ext, i64* %out, align 8
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ret void
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}
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