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Initial patch for supporting Hexagon DSP 

llvm-svn: 201665
This commit is contained in:
Deepak Panickal 2014-02-19 11:16:46 +00:00
parent 2274ba7716
commit 6d3df420d2
5 changed files with 24 additions and 2 deletions
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10
lldb/include/lldb/Core/ArchSpec.h
View File

@ -92,6 +92,10 @@ public:
eCore_x86_64_x86_64,
eCore_x86_64_x86_64h, // Haswell enabled x86_64
eCore_hexagon_generic,
eCore_hexagon_hexagonv4,
eCore_hexagon_hexagonv5,
eCore_uknownMach32,
eCore_uknownMach64,
kNumCores,
@ -103,6 +107,7 @@ public:
kCore_ppc_any,
kCore_ppc64_any,
kCore_x86_32_any,
kCore_hexagon_any,
kCore_arm_first = eCore_arm_generic,
kCore_arm_last = eCore_arm_xscale,
@ -117,7 +122,10 @@ public:
kCore_ppc64_last = eCore_ppc64_ppc970_64,
kCore_x86_32_first = eCore_x86_32_i386,
kCore_x86_32_last = eCore_x86_32_i486sx
kCore_x86_32_last = eCore_x86_32_i486sx,
kCore_hexagon_first = eCore_hexagon_generic,
kCore_hexagon_last = eCore_hexagon_hexagonv5
};
//------------------------------------------------------------------

11
lldb/source/Core/ArchSpec.cpp
View File

@ -105,6 +105,10 @@ static const CoreDefinition g_core_definitions[ArchSpec::kNumCores] =
{ eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64 , "x86_64" },
{ eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64 , ArchSpec::eCore_x86_64_x86_64h , "x86_64h" },
{ eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_generic, "hexagon" },
{ eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4" },
{ eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon , ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5" },
{ eByteOrderLittle, 4, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach32 , "unknown-mach-32" },
{ eByteOrderLittle, 8, 4, 4 , llvm::Triple::UnknownArch , ArchSpec::eCore_uknownMach64 , "unknown-mach-64" }
};
@ -237,7 +241,8 @@ static const ArchDefinitionEntry g_elf_arch_entries[] =
{ ArchSpec::eCore_arm_generic , llvm::ELF::EM_ARM , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // ARM
{ ArchSpec::eCore_sparc9_generic , llvm::ELF::EM_SPARCV9, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // SPARC V9
{ ArchSpec::eCore_x86_64_x86_64 , llvm::ELF::EM_X86_64 , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // AMD64
{ ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // MIPS
{ ArchSpec::eCore_mips64 , llvm::ELF::EM_MIPS , LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu }, // MIPS
{ ArchSpec::eCore_hexagon_generic , llvm::ELF::EM_HEXAGON, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu } // HEXAGON
};
static const ArchDefinition g_elf_arch_def = {
@ -919,6 +924,10 @@ cores_match (const ArchSpec::Core core1, const ArchSpec::Core core2, bool try_in
if (core2 == ArchSpec::eCore_arm_armv7)
return true;
}
case ArchSpec::kCore_hexagon_any:
if ((core2 >= ArchSpec::kCore_hexagon_first && core2 <= ArchSpec::kCore_hexagon_last) || (core2 == ArchSpec::kCore_hexagon_any))
return true;
break;
case ArchSpec::eCore_arm_armv7m:

2
lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
View File

@ -397,6 +397,8 @@ PlatformLinux::GetSoftwareBreakpointTrapOpcode (Target &target,
trap_opcode_size = sizeof(g_i386_breakpoint_opcode);
}
break;
case ArchSpec::eCore_hexagon_generic:
return 0;
}
if (bp_site->SetTrapOpcode(trap_opcode, trap_opcode_size))

2
lldb/source/Plugins/Platform/Windows/PlatformWindows.cpp
View File

@ -291,6 +291,8 @@ PlatformWindows::GetSoftwareBreakpointTrapOpcode (Target &target, BreakpointSite
}
break;
case ArchSpec::eCore_hexagon_generic:
return 0;
default:
llvm_unreachable("Unhandled architecture in PlatformWindows::GetSoftwareBreakpointTrapOpcode()");
break;

1
lldb/source/Target/Thread.cpp
View File

@ -2023,6 +2023,7 @@ Thread::GetUnwinder ()
case llvm::Triple::arm:
case llvm::Triple::thumb:
case llvm::Triple::mips64:
case llvm::Triple::hexagon:
m_unwinder_ap.reset (new UnwindLLDB (*this));
break;