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Remove unnecessary call to getAllocatableRegClass 

This reapplies r252565 and r252674, effectively reverting r252956.

This allows VS_32/VS_64 to be unallocatable like they should be.

llvm-svn: 280783
This commit is contained in:
Matt Arsenault 2016-09-07 06:16:45 +00:00
parent 0e473955a0
commit 6cda10c950
3 changed files with 19 additions and 18 deletions
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24
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
View File

@ -330,16 +330,22 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
// shrink VReg's register class within reason. For example, if VReg == GR32
// and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
if (II) {
const TargetRegisterClass *DstRC = nullptr;
const TargetRegisterClass *OpRC = nullptr;
if (IIOpNum < II->getNumOperands())
DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) &&
"Expected VReg");
if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
unsigned NewVReg = MRI->createVirtualRegister(DstRC);
BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
VReg = NewVReg;
OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
if (OpRC) {
const TargetRegisterClass *ConstrainedRC
= MRI->constrainRegClass(VReg, OpRC, MinRCSize);
if (!ConstrainedRC) {
unsigned NewVReg = MRI->createVirtualRegister(OpRC);
BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
VReg = NewVReg;
} else {
assert(ConstrainedRC->isAllocatable() &&
"Constraining an allocatable VReg produced an unallocatable class?");
}
}
}

7
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
View File

@ -107,13 +107,6 @@ public:
/// \returns true if this class contains VGPR registers.
bool hasVGPRs(const TargetRegisterClass *RC) const;
/// returns true if this is a pseudoregister class combination of VGPRs and
/// SGPRs for operand modeling. FIXME: We should set isAllocatable = 0 on
/// them.
static bool isPseudoRegClass(const TargetRegisterClass *RC) {
return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass;
}
/// \returns A VGPR reg class with the same width as \p SRC
const TargetRegisterClass *getEquivalentVGPRClass(
const TargetRegisterClass *SRC) const;

6
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
View File

@ -346,10 +346,12 @@ def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
let Size = 32;
}
def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)> {
let isAllocatable = 0;
}
def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
let CopyCost = 2;
let isAllocatable = 0;
}
//===----------------------------------------------------------------------===//