[Power9] Processor Model for Scheduling
PWR9 processor model for instruction scheduling. A subsequent patch will migrate PWR9 to Post RA MIScheduler. https://reviews.llvm.org/D24525 llvm-svn: 290102
This commit is contained in:
Ehsan Amiri
parent
c0eb996318
commit
6c17bb0eb7
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//===- P9InstrResources.td - P9 Instruction Resource Defs -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines resources required by some of P9 instruction. This is part
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// P9 processor model used for instruction scheduling. Not every instruction
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// is listed here. Instructions in this file belong to itinerary classes that
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// have instructions with different resource requirements.
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//
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//===----------------------------------------------------------------------===//
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def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
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DISP_1C, DISP_1C],
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(instrs
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VADDCUW,
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VADDUBM,
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VADDUDM,
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VADDUHM,
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VADDUWM,
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VAND,
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VANDC,
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VCMPEQUB,
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VCMPEQUBo,
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VCMPEQUD,
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VCMPEQUDo,
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VCMPEQUH,
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VCMPEQUHo,
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VCMPEQUW,
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VCMPEQUWo,
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VCMPGTSB,
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VCMPGTSBo,
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VCMPGTSD,
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VCMPGTSDo,
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VCMPGTSH,
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VCMPGTSHo,
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VCMPGTSW,
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VCMPGTSWo,
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VCMPGTUB,
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VCMPGTUBo,
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VCMPGTUD,
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VCMPGTUDo,
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VCMPGTUH,
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VCMPGTUHo,
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VCMPGTUW,
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VCMPGTUWo,
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VCMPNEB,
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VCMPNEBo,
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VCMPNEH,
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VCMPNEHo,
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VCMPNEW,
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VCMPNEWo,
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VCMPNEZB,
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VCMPNEZBo,
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VCMPNEZH,
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VCMPNEZHo,
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VCMPNEZW,
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VCMPNEZWo,
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VEQV,
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VEXTSB2D,
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VEXTSB2W,
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VEXTSH2D,
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VEXTSH2W,
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VEXTSW2D,
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VMRGEW,
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VMRGOW,
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VNAND,
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VNEGD,
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VNEGW,
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VNOR,
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VOR,
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VORC,
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VPOPCNTB,
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VPOPCNTH,
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VPOPCNTW,
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VSEL,
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VSUBCUW,
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VSUBUBM,
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VSUBUDM,
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VSUBUHM,
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VSUBUWM,
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VXOR,
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V_SET0B,
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V_SET0H,
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V_SET0,
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XVABSDP,
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XVABSSP,
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XVCPSGNDP,
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XVCPSGNSP,
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XVIEXPDP,
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XVNABSDP,
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XVNABSSP,
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XVNEGDP,
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XVNEGSP,
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XVXEXPDP,
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XXLAND,
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XXLANDC,
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XXLEQV,
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XXLNAND,
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XXLNOR,
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XXLOR,
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XXLORf,
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XXLORC,
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XXLXOR,
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XXSEL
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)>;
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def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
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(instrs
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XSABSQP,
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XSCPSGNQP,
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XSIEXPQP,
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XSNABSQP,
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XSNEGQP,
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XSXEXPQP,
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XSABSDP,
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XSCPSGNDP,
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XSIEXPDP,
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XSNABSDP,
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XSNEGDP,
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XSXEXPDP
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)>;
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def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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(instrs
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VMINSB,
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VMINSD,
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VMINSH,
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VMINSW,
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VMINUB,
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VMINUD,
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VMINUH,
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VMINUW,
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VPOPCNTD,
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VPRTYBD,
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VPRTYBW,
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VRLB,
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VRLD,
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VRLDMI,
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VRLDNM,
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VRLH,
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VRLW,
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VRLWMI,
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VRLWNM,
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VSHASIGMAD,
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VSHASIGMAW,
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VSLB,
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VSLD,
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VSLH,
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VSLW,
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VSRAB,
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VSRAD,
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VSRAH,
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VSRAW,
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VSRB,
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VSRD,
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VSRH,
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VSRW,
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VSUBSBS,
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VSUBSHS,
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VSUBSWS,
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VSUBUBS,
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VSUBUHS,
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VSUBUWS,
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XSCMPEQDP,
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XSCMPEXPDP,
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XSCMPGEDP,
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XSCMPGTDP,
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XSCMPODP,
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XSCMPUDP,
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XSCVSPDPN,
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XSMAXCDP,
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XSMAXDP,
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XSMAXJDP,
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XSMINCDP,
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XSMINDP,
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XSMINJDP,
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XSTDIVDP,
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XSTSQRTDP,
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XSTSTDCDP,
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XSTSTDCSP,
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XSXSIGDP,
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XVCMPEQDP,
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XVCMPEQDPo,
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XVCMPEQSP,
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XVCMPEQSPo,
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XVCMPGEDP,
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XVCMPGEDPo,
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XVCMPGESP,
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XVCMPGESPo,
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XVCMPGTDP,
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XVCMPGTDPo,
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XVCMPGTSP,
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XVCMPGTSPo,
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XVIEXPSP,
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XVMAXDP,
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XVMAXSP,
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XVMINDP,
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XVMINSP,
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XVTDIVDP,
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XVTDIVSP,
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XVTSQRTDP,
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XVTSQRTSP,
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XVTSTDCDP,
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XVTSTDCSP,
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XVXEXPSP,
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XVXSIGDP,
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XVXSIGSP
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)>;
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def : InstRW<[P9_ALUE_4C, P9_ALUO_4C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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(instrs
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VABSDUB,
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VABSDUH,
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VABSDUW,
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VADDSBS,
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VADDSHS,
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VADDSWS,
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VADDUBS,
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VADDUHS,
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VADDUWS,
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VAVGSB,
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VAVGSH,
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VAVGSW,
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VAVGUB,
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VAVGUH,
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VAVGUW,
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VBPERMD,
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VCLZB,
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VCLZD,
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VCLZH,
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VCLZW,
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VCMPBFP,
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VCMPBFPo,
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VCMPGTFP,
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VCMPGTFPo,
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VCTZB,
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VCTZD,
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VCTZH,
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VCTZW,
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VMAXFP,
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VMAXSB,
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VMAXSD,
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VMAXSH,
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VMAXSW,
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VMAXUB,
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VMAXUD,
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VMAXUH,
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VMAXUW,
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VMINFP,
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VCMPEQFP,
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VCMPEQFPo,
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VCMPGEFP,
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VCMPGEFPo
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)>;
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def : InstRW<[P9_DPE_7C, P9_DPO_7C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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(instrs
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VADDFP,
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VCTSXS,
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VCTSXS_0,
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VCTUXS,
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VCTUXS_0,
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VEXPTEFP,
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VLOGEFP,
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VMADDFP,
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VMHADDSHS,
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VNMSUBFP,
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VREFP,
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VRFIM,
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VRFIN,
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VRFIP,
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VRFIZ,
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VRSQRTEFP,
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VSUBFP,
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XVADDDP,
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XVADDSP,
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XVCVDPSP,
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XVCVDPSXDS,
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XVCVDPSXWS,
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XVCVDPUXDS,
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XVCVDPUXWS,
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XVCVHPSP,
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XVCVSPDP,
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XVCVSPHP,
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XVCVSPSXDS,
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XVCVSPSXWS,
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XVCVSPUXDS,
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XVCVSPUXWS,
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XVCVSXDDP,
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XVCVSXDSP,
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XVCVSXWDP,
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XVCVSXWSP,
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XVCVUXDDP,
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XVCVUXDSP,
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XVCVUXWDP,
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XVCVUXWSP,
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XVMADDADP,
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XVMADDASP,
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XVMADDMDP,
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XVMADDMSP,
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XVMSUBADP,
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XVMSUBASP,
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XVMSUBMDP,
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XVMSUBMSP,
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XVMULDP,
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XVMULSP,
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XVNMADDADP,
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XVNMADDASP,
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XVNMADDMDP,
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XVNMADDMSP,
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XVNMSUBADP,
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XVNMSUBASP,
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XVNMSUBMDP,
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XVNMSUBMSP,
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XVRDPI,
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XVRDPIC,
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XVRDPIM,
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XVRDPIP,
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XVRDPIZ,
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XVREDP,
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XVRESP,
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XVRSPI,
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XVRSPIC,
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XVRSPIM,
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XVRSPIP,
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XVRSPIZ,
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XVRSQRTEDP,
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XVRSQRTESP,
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XVSUBDP,
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XVSUBSP,
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VCFSX,
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VCFSX_0,
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VCFUX,
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VCFUX_0,
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VMHRADDSHS,
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VMLADDUHM,
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VMSUMMBM,
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VMSUMSHM,
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VMSUMSHS,
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VMSUMUBM,
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VMSUMUHM,
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VMSUMUHS,
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VMULESB,
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VMULESH,
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VMULESW,
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VMULEUB,
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VMULEUH,
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VMULEUW,
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VMULOSB,
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VMULOSH,
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VMULOSW,
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VMULOUB,
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VMULOUH,
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VMULOUW,
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VMULUWM,
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VSUM2SWS,
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VSUM4SBS,
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VSUM4SHS,
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VSUM4UBS,
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VSUMSWS
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)>;
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def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
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(instrs
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XSMADDADP,
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XSMADDASP,
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XSMADDMDP,
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XSMADDMSP,
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XSMSUBADP,
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XSMSUBASP,
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XSMSUBMDP,
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XSMSUBMSP,
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XSMULDP,
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XSMULSP,
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XSNMADDADP,
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XSNMADDASP,
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XSNMADDMDP,
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XSNMADDMSP,
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XSNMSUBADP,
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XSNMSUBASP,
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XSNMSUBMDP,
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XSNMSUBMSP
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)>;
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def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C],
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(instrs
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XSADDDP,
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XSADDSP,
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XSCVDPHP,
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XSCVDPSP,
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XSCVDPSXDS,
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XSCVDPSXWS,
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XSCVDPUXDS,
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XSCVDPUXWS,
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XSCVHPDP,
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XSCVSPDP,
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XSCVSXDDP,
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XSCVSXDSP,
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XSCVUXDDP,
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XSCVUXDSP,
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XSRDPI,
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XSRDPIC,
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XSRDPIM,
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XSRDPIP,
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XSRDPIZ,
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XSREDP,
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XSRESP,
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//XSRSP,
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XSRSQRTEDP,
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XSRSQRTESP,
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XSSUBDP,
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XSSUBSP,
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XSCVDPSPN
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)>;
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def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C],
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(instrs
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VBPERMQ,
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VCLZLSBB,
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VCTZLSBB,
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VEXTRACTD,
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VEXTRACTUB,
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VEXTRACTUH,
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VEXTRACTUW,
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VEXTUBLX,
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VEXTUBRX,
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VEXTUHLX,
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VEXTUHRX,
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VEXTUWLX,
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VEXTUWRX,
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VGBBD,
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VINSERTB,
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VINSERTD,
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VINSERTH,
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VINSERTW,
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VMRGHB,
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VMRGHH,
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VMRGHW,
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VMRGLB,
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VMRGLH,
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VMRGLW,
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VPERM,
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VPERMR,
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VPERMXOR,
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VPKPX,
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VPKSDSS,
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VPKSDUS,
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VPKSHSS,
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VPKSHUS,
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VPKSWSS,
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VPKSWUS,
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VPKUDUM,
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VPKUDUS,
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VPKUHUM,
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VPKUHUS,
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VPKUWUM,
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VPKUWUS,
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VPRTYBQ,
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VSL,
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VSLDOI,
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VSLO,
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VSLV,
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VSPLTB,
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VSPLTH,
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VSPLTISB,
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VSPLTISH,
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VSPLTISW,
|
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VSPLTW,
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VSR,
|
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VSRO,
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VSRV,
|
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VUPKHPX,
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VUPKHSB,
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VUPKHSH,
|
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VUPKHSW,
|
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VUPKLPX,
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VUPKLSB,
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VUPKLSH,
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VUPKLSW,
|
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XXBRD,
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XXBRH,
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XXBRQ,
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XXBRW,
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XXEXTRACTUW,
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XXINSERTW,
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XXMRGHW,
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XXMRGLW,
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XXPERM,
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XXPERMR,
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XXSLDWI,
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XXSPLTIB,
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XXSPLTW,
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VADDCUQ,
|
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VADDECUQ,
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VADDEUQM,
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VADDUQM,
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VMUL10CUQ,
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VMUL10ECUQ,
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VMUL10EUQ,
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VMUL10UQ,
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VSUBCUQ,
|
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VSUBECUQ,
|
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VSUBEUQM,
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VSUBUQM,
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XSCMPEXPQP,
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XSCMPOQP,
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XSCMPUQP,
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XSTSTDCQP,
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XSXSIGQP
|
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)>;
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def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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(instrs
|
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XSADDQP,
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XSADDQPO,
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XSCVDPQP,
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XSCVQPDP,
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XSCVQPDPO,
|
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XSCVQPSDZ,
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XSCVQPSWZ,
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XSCVQPUDZ,
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XSCVQPUWZ,
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XSCVSDQP,
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XSCVUDQP,
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XSRQPI,
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XSRQPXP,
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XSSUBQP,
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||||
XSSUBQPO
|
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)>;
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||||
|
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def : InstRW<[P9_DFU_24C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
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(instrs
|
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XSMADDQP,
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XSMADDQPO,
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XSMSUBQP,
|
||||
XSMSUBQPO,
|
||||
XSMULQP,
|
||||
XSMULQPO,
|
||||
XSNMADDQP,
|
||||
XSNMADDQPO,
|
||||
XSNMSUBQP,
|
||||
XSNMSUBQPO
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DFU_58C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSDIVQP,
|
||||
XSDIVQPO
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DFU_76C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XSSQRTQP,
|
||||
XSSQRTQPO
|
||||
)>;
|
||||
|
||||
// Load Operation in IIC_LdStLFD
|
||||
|
||||
def : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LXSDX,
|
||||
LXVD2X,
|
||||
LXSIWZX,
|
||||
LXV,
|
||||
LXSD
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LFIWZX,
|
||||
LFDX,
|
||||
LFD
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LXSSPX,
|
||||
LXSIWAX,
|
||||
LXSSP
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LFIWAX,
|
||||
LFSX,
|
||||
LFS
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LXVDSX,
|
||||
LXVW4X
|
||||
)>;
|
||||
|
||||
// Store Operations in IIC_LdStSTFD.
|
||||
|
||||
def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
STFS,
|
||||
STFD,
|
||||
STFIWX,
|
||||
STFSX,
|
||||
STFDX,
|
||||
STXSDX,
|
||||
STXSSPX,
|
||||
STXSIWX
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
STXVD2X,
|
||||
STXVW4X
|
||||
)>;
|
||||
|
||||
|
||||
// Divide Operations in IIC_IntDivW, IIC_IntDivD.
|
||||
|
||||
def : InstRW<[P9_DIV_16C_8, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVW,
|
||||
DIVWU
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DIV_24C_8, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVWE,
|
||||
DIVD,
|
||||
DIVWEU,
|
||||
DIVDU
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DIV_40C_8, IP_EXECE_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVDE,
|
||||
DIVDEU
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVWEo,
|
||||
DIVWEUo
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
DIVDEo,
|
||||
DIVDEUo
|
||||
)>;
|
||||
|
||||
// Rotate Operations in IIC_IntRotateD, IIC_IntRotateDI
|
||||
def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
SLD,
|
||||
SRD,
|
||||
SRAD,
|
||||
SRADI,
|
||||
RLDIC
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
RLDCL,
|
||||
RLDCR,
|
||||
RLDIMI,
|
||||
RLDICL,
|
||||
RLDICR,
|
||||
RLDICL_32_64
|
||||
)>;
|
||||
|
||||
// CR access instructions in _BrMCR, IIC_BrMCRX.
|
||||
|
||||
def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
MTOCRF,
|
||||
MTOCRF8,
|
||||
MTCRF,
|
||||
MTCRF8
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_ALU_5C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
MCRF,
|
||||
MCRXRX
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_ALU_5C, P9_ALU_5C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
MCRFS
|
||||
)>;
|
||||
|
||||
// FP Div instructions in IIC_FPDivD and IIC_FPDivS.
|
||||
|
||||
def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FDIV,
|
||||
XSDIVDP
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DP_22C_5, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FDIVS,
|
||||
XSDIVSP
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DP_24C_8, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XVDIVSP
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DP_33C_8, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
XVDIVDP
|
||||
)>;
|
||||
|
||||
// FP Instructions in IIC_FPGeneral, IIC_FPFused
|
||||
|
||||
def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FRSP,
|
||||
FRIND,
|
||||
FRINS,
|
||||
FRIPD,
|
||||
FRIPS,
|
||||
FRIZD,
|
||||
FRIZS,
|
||||
FRIMD,
|
||||
FRIMS,
|
||||
FRE,
|
||||
FRES,
|
||||
FRSQRTE,
|
||||
FRSQRTES,
|
||||
FMADDS,
|
||||
FMADD,
|
||||
FMSUBS,
|
||||
FMSUB,
|
||||
FNMADDS,
|
||||
FNMADD,
|
||||
FNMSUBS,
|
||||
FNMSUB,
|
||||
FSELD,
|
||||
FSELS,
|
||||
FADDS,
|
||||
FMULS,
|
||||
FMUL,
|
||||
FSUBS,
|
||||
FCFID,
|
||||
FCTID,
|
||||
FCTIDZ,
|
||||
FCFIDU,
|
||||
FCFIDS,
|
||||
FCFIDUS,
|
||||
FCTIDUZ,
|
||||
FCTIWUZ,
|
||||
FCTIW,
|
||||
FCTIWZ
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FMR,
|
||||
FABSD,
|
||||
FABSS,
|
||||
FNABSD,
|
||||
FNABSS,
|
||||
FNEGD,
|
||||
FNEGS,
|
||||
FCPSGND,
|
||||
FCPSGNS
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
FCMPUS,
|
||||
FCMPUD
|
||||
)>;
|
||||
|
||||
// Load instructions in IIC_LdStLFDU and IIC_LdStLFDUX.
|
||||
|
||||
def : InstRW<[P9_LoadAndALUOp_7C, P9_ALU_2C,
|
||||
IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LFSU,
|
||||
LFSUX
|
||||
)>;
|
||||
|
||||
def : InstRW<[P9_LS_5C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
(instrs
|
||||
LFDU,
|
||||
LFDUX
|
||||
)>;
|
||||
|
||||
|
|
@ -289,7 +289,6 @@ def getAltVSXFMAOpcode : InstrMapping {
|
|||
|
||||
include "PPCRegisterInfo.td"
|
||||
include "PPCSchedule.td"
|
||||
include "PPCInstrInfo.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// PowerPC processors supported.
|
||||
|
|
@ -418,8 +417,7 @@ def : ProcessorModel<"pwr6x", G5Model,
|
|||
FeatureMFTB, DeprecatedDST]>;
|
||||
def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
|
||||
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
|
||||
// FIXME: Same as P8 until the POWER9 scheduling info is available
|
||||
def : ProcessorModel<"pwr9", P8Model, ProcessorFeatures.Power9FeatureList>;
|
||||
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
|
||||
def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
|
||||
FeatureMFTB]>;
|
||||
def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
|
||||
|
|
|
|||
|
|
@ -129,6 +129,7 @@ include "PPCScheduleG4Plus.td"
|
|||
include "PPCScheduleG5.td"
|
||||
include "PPCScheduleP7.td"
|
||||
include "PPCScheduleP8.td"
|
||||
include "PPCScheduleP9.td"
|
||||
include "PPCScheduleA2.td"
|
||||
include "PPCScheduleE500mc.td"
|
||||
include "PPCScheduleE5500.td"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,335 @@
|
|||
//===-- PPCScheduleP9.td - PPC P9 Scheduling Definitions ---*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the itinerary class data for the POWER9 processor.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
include "PPCInstrInfo.td"
|
||||
|
||||
def P9Model : SchedMachineModel {
|
||||
let IssueWidth = 8;
|
||||
|
||||
let LoadLatency = 5;
|
||||
|
||||
let MispredictPenalty = 16;
|
||||
|
||||
// Try to make sure we have at least 10 dispatch groups in a loop.
|
||||
let LoopMicroOpBufferSize = 60;
|
||||
|
||||
let CompleteModel = 0;
|
||||
|
||||
}
|
||||
|
||||
let SchedModel = P9Model in {
|
||||
|
||||
// ***************** Processor Resources *****************
|
||||
|
||||
//Dispatcher:
|
||||
def DISPATCHER : ProcResource<12>;
|
||||
|
||||
// Issue Ports
|
||||
def IP_AGEN : ProcResource<4>;
|
||||
def IP_EXEC : ProcResource<4>;
|
||||
def IP_EXECE : ProcResource<2> {
|
||||
//Even Exec Ports
|
||||
let Super = IP_EXEC;
|
||||
}
|
||||
def IP_EXECO : ProcResource<2> {
|
||||
//Odd Exec Ports
|
||||
let Super = IP_EXEC;
|
||||
}
|
||||
|
||||
// Pipeline Groups
|
||||
def ALU : ProcResource<4>;
|
||||
def ALUE : ProcResource<2> {
|
||||
//Even ALU pipelines
|
||||
let Super = ALU;
|
||||
}
|
||||
def ALUO : ProcResource<2> {
|
||||
//Odd ALU pipelines
|
||||
let Super = ALU;
|
||||
}
|
||||
def DIV : ProcResource<2>;
|
||||
def DP : ProcResource<4>;
|
||||
def DPE : ProcResource<2> {
|
||||
//Even DP pipelines
|
||||
let Super = DP;
|
||||
}
|
||||
def DPO : ProcResource<2> {
|
||||
//Odd DP pipelines
|
||||
let Super = DP;
|
||||
}
|
||||
def LS : ProcResource<4>;
|
||||
def PM : ProcResource<2>;
|
||||
def DFU : ProcResource<1>;
|
||||
|
||||
def TestGroup : ProcResGroup<[ALU, DP]>;
|
||||
|
||||
// ***************** SchedWriteRes Definitions *****************
|
||||
|
||||
//Dispatcher
|
||||
def DISP_1C : SchedWriteRes<[DISPATCHER]> {
|
||||
let NumMicroOps = 0;
|
||||
let Latency = 1;
|
||||
}
|
||||
|
||||
// Issue Ports
|
||||
def IP_AGEN_1C : SchedWriteRes<[IP_AGEN]> {
|
||||
let NumMicroOps = 0;
|
||||
let Latency = 1;
|
||||
}
|
||||
|
||||
def IP_EXEC_1C : SchedWriteRes<[IP_EXEC]> {
|
||||
let NumMicroOps = 0;
|
||||
let Latency = 1;
|
||||
}
|
||||
|
||||
def IP_EXECE_1C : SchedWriteRes<[IP_EXECE]> {
|
||||
let NumMicroOps = 0;
|
||||
let Latency = 1;
|
||||
}
|
||||
|
||||
def IP_EXECO_1C : SchedWriteRes<[IP_EXECO]> {
|
||||
let NumMicroOps = 0;
|
||||
let Latency = 1;
|
||||
}
|
||||
|
||||
//Pipeline Groups
|
||||
def P9_ALU_2C : SchedWriteRes<[ALU]> {
|
||||
let Latency = 2;
|
||||
}
|
||||
|
||||
def P9_ALUE_2C : SchedWriteRes<[ALUE]> {
|
||||
let Latency = 2;
|
||||
}
|
||||
|
||||
def P9_ALUO_2C : SchedWriteRes<[ALUO]> {
|
||||
let Latency = 2;
|
||||
}
|
||||
|
||||
def P9_ALU_3C : SchedWriteRes<[ALU]> {
|
||||
let Latency = 3;
|
||||
}
|
||||
|
||||
def P9_ALUE_3C : SchedWriteRes<[ALUE]> {
|
||||
let Latency = 3;
|
||||
}
|
||||
|
||||
def P9_ALUO_3C : SchedWriteRes<[ALUO]> {
|
||||
let Latency = 3;
|
||||
}
|
||||
|
||||
def P9_ALU_4C : SchedWriteRes<[ALU]> {
|
||||
let Latency = 4;
|
||||
}
|
||||
|
||||
def P9_ALUE_4C : SchedWriteRes<[ALUE]> {
|
||||
let Latency = 4;
|
||||
}
|
||||
|
||||
def P9_ALUO_4C : SchedWriteRes<[ALUO]> {
|
||||
let Latency = 4;
|
||||
}
|
||||
|
||||
def P9_ALU_5C : SchedWriteRes<[ALU]> {
|
||||
let Latency = 5;
|
||||
}
|
||||
|
||||
def P9_ALU_6C : SchedWriteRes<[ALU]> {
|
||||
let Latency = 6;
|
||||
}
|
||||
|
||||
def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 16;
|
||||
}
|
||||
|
||||
def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 24;
|
||||
}
|
||||
|
||||
def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 40;
|
||||
}
|
||||
|
||||
def P9_DP_2C : SchedWriteRes<[DP]> {
|
||||
let Latency = 2;
|
||||
}
|
||||
|
||||
def P9_DP_5C : SchedWriteRes<[DP]> {
|
||||
let Latency = 5;
|
||||
}
|
||||
|
||||
def P9_DP_7C : SchedWriteRes<[DP]> {
|
||||
let Latency = 7;
|
||||
}
|
||||
|
||||
def P9_DPE_7C : SchedWriteRes<[DPE]> {
|
||||
let Latency = 7;
|
||||
}
|
||||
|
||||
def P9_DPO_7C : SchedWriteRes<[DPO]> {
|
||||
let Latency = 7;
|
||||
}
|
||||
|
||||
def P9_DP_22C_5 : SchedWriteRes<[DP]> {
|
||||
let ResourceCycles = [5];
|
||||
let Latency = 22;
|
||||
}
|
||||
|
||||
def P9_DP_24C_8 : SchedWriteRes<[DP]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 24;
|
||||
}
|
||||
|
||||
def P9_DP_26C_5 : SchedWriteRes<[DP]> {
|
||||
let ResourceCycles = [5];
|
||||
let Latency = 22;
|
||||
}
|
||||
|
||||
def P9_DP_27C_7 : SchedWriteRes<[DP]> {
|
||||
let ResourceCycles = [7];
|
||||
let Latency = 27;
|
||||
}
|
||||
|
||||
def P9_DP_33C_8 : SchedWriteRes<[DP]> {
|
||||
let ResourceCycles = [8];
|
||||
let Latency = 33;
|
||||
}
|
||||
|
||||
def P9_DP_36C_10 : SchedWriteRes<[DP]> {
|
||||
let ResourceCycles = [10];
|
||||
let Latency = 36;
|
||||
}
|
||||
|
||||
def P9_PM_3C : SchedWriteRes<[PM]> {
|
||||
let Latency = 3;
|
||||
}
|
||||
|
||||
def P9_PM_7C : SchedWriteRes<[PM]> {
|
||||
let Latency = 3;
|
||||
}
|
||||
|
||||
def P9_LS_1C : SchedWriteRes<[LS]> {
|
||||
let Latency = 1;
|
||||
}
|
||||
|
||||
def P9_LS_4C : SchedWriteRes<[LS]> {
|
||||
let Latency = 4;
|
||||
}
|
||||
|
||||
def P9_LS_5C : SchedWriteRes<[LS]> {
|
||||
let Latency = 5;
|
||||
}
|
||||
|
||||
def P9_DFU_12C : SchedWriteRes<[DFU]> {
|
||||
let Latency = 12;
|
||||
}
|
||||
|
||||
def P9_DFU_24C : SchedWriteRes<[DFU]> {
|
||||
let Latency = 24;
|
||||
let ResourceCycles = [12];
|
||||
}
|
||||
|
||||
def P9_DFU_58C : SchedWriteRes<[DFU]> {
|
||||
let Latency = 58;
|
||||
let ResourceCycles = [44];
|
||||
}
|
||||
|
||||
def P9_DFU_76C : SchedWriteRes<[TestGroup, DFU]> {
|
||||
let Latency = 76;
|
||||
let ResourceCycles = [62];
|
||||
}
|
||||
// ***************** WriteSeq Definitions *****************
|
||||
|
||||
def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
|
||||
def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
|
||||
def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
|
||||
def P9_IntDivAndALUOp_26C_8 : WriteSequence<[P9_DIV_24C_8, P9_ALU_2C]>;
|
||||
def P9_IntDivAndALUOp_42C_8 : WriteSequence<[P9_DIV_40C_8, P9_ALU_2C]>;
|
||||
def P9_StoreAndALUOp_4C : WriteSequence<[P9_LS_1C, P9_ALU_3C]>;
|
||||
def P9_ALUOpAndALUOp_4C : WriteSequence<[P9_ALU_2C, P9_ALU_2C]>;
|
||||
|
||||
// ***************** Defining Itinerary Class Resources *****************
|
||||
|
||||
def : ItinRW<[P9_DFU_76C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple,
|
||||
IIC_IntGeneral]>;
|
||||
|
||||
def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_IntISEL, IIC_IntRotate, IIC_IntShift]>;
|
||||
|
||||
def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntCompare]>;
|
||||
|
||||
def : ItinRW<[P9_DP_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_IntMulHW, IIC_IntMulHWU, IIC_IntMulLI]>;
|
||||
|
||||
def : ItinRW<[P9_LS_5C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStLoad, IIC_LdStLD]>;
|
||||
|
||||
def : ItinRW<[P9_LS_4C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStLoadUpd, IIC_LdStLDU]>;
|
||||
|
||||
def : ItinRW<[P9_LS_4C, P9_ALU_2C, IP_EXECE_1C, IP_EXECO_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStLoadUpdX, IIC_LdStLDUX]>;
|
||||
|
||||
def : ItinRW<[P9_LS_1C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStSTFDU]>;
|
||||
|
||||
def : ItinRW<[P9_LoadAndALUOp_6C,
|
||||
IP_AGEN_1C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStLHA, IIC_LdStLWA]>;
|
||||
|
||||
def : ItinRW<[P9_LoadAndALUOp_6C, P9_ALU_2C,
|
||||
IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStLHAU, IIC_LdStLHAUX]>;
|
||||
|
||||
// IIC_LdStLMW contains two microcoded insns. This is not accurate, but
|
||||
// those insns are not used that much, if at all.
|
||||
def : ItinRW<[P9_LS_4C, IP_EXEC_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStLWARX, IIC_LdStLDARX, IIC_LdStLMW]>;
|
||||
|
||||
def : ItinRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStSTFD, IIC_LdStSTD, IIC_LdStStore]>;
|
||||
|
||||
def : ItinRW<[P9_LS_1C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStSTDU, IIC_LdStSTDUX]>;
|
||||
|
||||
def : ItinRW<[P9_StoreAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_LdStSTDCX, IIC_LdStSTWCX]>;
|
||||
|
||||
def : ItinRW<[P9_ALU_5C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
|
||||
[IIC_BrCR, IIC_IntMTFSB0]>;
|
||||
|
||||
def : ItinRW<[P9_ALUOpAndALUOp_4C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
|
||||
IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C], [IIC_SprMFCR, IIC_SprMFCRF]>;
|
||||
|
||||
// This class should be broken down to instruction level, once some missing
|
||||
// info is obtained.
|
||||
def : ItinRW<[P9_LoadAndALUOp_6C, IP_EXEC_1C, IP_AGEN_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C], [IIC_SprMTSPR]>;
|
||||
|
||||
def : ItinRW<[P9_DP_7C, IP_EXEC_1C,
|
||||
DISP_1C, DISP_1C, DISP_1C], [IIC_FPGeneral, IIC_FPAddSub]>;
|
||||
|
||||
def : ItinRW<[P9_DP_36C_10, IP_EXEC_1C], [IIC_FPSqrtD]>;
|
||||
def : ItinRW<[P9_DP_26C_5, P9_DP_26C_5, IP_EXEC_1C, IP_EXEC_1C], [IIC_FPSqrtS]>;
|
||||
|
||||
include "P9InstrResources.td"
|
||||
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue