AMDGPU: Make findUsedSGPR more readable
Add more comments etc. llvm-svn: 251996
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@ -2665,6 +2665,7 @@ const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
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}
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}
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// Find the one SGPR operand we are allowed to use.
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unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
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int OpIndices[3]) const {
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const MCInstrDesc &Desc = MI->getDesc();
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@ -2691,16 +2692,23 @@ unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
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break;
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const MachineOperand &MO = MI->getOperand(Idx);
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if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
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SGPRReg = MO.getReg();
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if (!MO.isReg())
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continue;
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if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
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UsedSGPRs[i] = MO.getReg();
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// Is this operand statically required to be an SGPR based on the operand
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// constraints?
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const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
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bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
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if (IsRequiredSGPR)
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return MO.getReg();
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// If this could be a VGPR or an SGPR, Check the dynamic register class.
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unsigned Reg = MO.getReg();
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const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
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if (RI.isSGPRClass(RegRC))
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UsedSGPRs[i] = Reg;
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}
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if (SGPRReg != AMDGPU::NoRegister)
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return SGPRReg;
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// We don't have a required SGPR operand, so we have a bit more freedom in
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// selecting operands to move.
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@ -2711,6 +2719,9 @@ unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
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// V_FMA_F32 v0, s0, s0, s0 -> No moves
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// V_FMA_F32 v0, s0, s1, s0 -> Move s1
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// TODO: If some of the operands are 64-bit SGPRs and some 32, we should
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// prefer those.
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if (UsedSGPRs[0] != AMDGPU::NoRegister) {
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if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
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SGPRReg = UsedSGPRs[0];
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