Fix bugs which were introduced when support for base+index floating point loads
and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
This commit is contained in:
Akira Hatanaka
parent
f7e02a0cab
commit
6bbe1f0d10
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@ -202,6 +202,21 @@ bool MipsDAGToDAGISel::
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SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
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EVT ValTy = Addr.getValueType();
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// If Parent is an unaligned f32 load or store, select a (base + index)
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// floating point load/store instruction (luxc1 or suxc1).
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const LSBaseSDNode* LS = 0;
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if (Parent && (LS = dyn_cast<LSBaseSDNode>(Parent))) {
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EVT VT = LS->getMemoryVT();
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if (VT.getSizeInBits() / 8 > LS->getAlignment()) {
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assert(TLI.allowsUnalignedMemoryAccesses(VT) &&
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"Unaligned loads/stores not supported for this type.");
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if (VT == MVT::f32)
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return false;
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}
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}
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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@ -259,11 +274,10 @@ SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
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}
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}
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// If an indexed load/store can be emitted, return false.
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if (const LSBaseSDNode* LS = dyn_cast<LSBaseSDNode>(Parent))
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if ((LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
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Subtarget.hasMips32r2Or64())
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return false;
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// If an indexed floating point load/store can be emitted, return false.
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if (LS && (LS->getMemoryVT() == MVT::f32 || LS->getMemoryVT() == MVT::f64) &&
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Subtarget.hasMips32r2Or64())
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return false;
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}
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Base = Addr;
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@ -268,7 +268,6 @@ bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
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case MVT::i16:
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return true;
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case MVT::f32:
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case MVT::f64:
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return Subtarget->hasMips32r2Or64();
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default:
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return false;
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@ -85,13 +85,13 @@ def fpimm0neg : PatLeaf<(fpimm), [{
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// FP load.
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class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
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FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
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!strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))],
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!strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load_a addr:$addr))],
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IILoad>;
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// FP store.
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class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>:
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FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
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!strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
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!strconcat(opstr, "\t$ft, $addr"), [(store_a RC:$ft, addr:$addr)],
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IIStore>;
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// FP indexed load.
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@ -433,3 +433,16 @@ let Predicates = [IsFP64bit] in {
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def : Pat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>;
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def : Pat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>;
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}
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// Patterns for unaligned floating point loads and stores.
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let Predicates = [HasMips32r2Or64, NotN64] in {
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def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
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def : Pat<(store_u FGR32:$src, CPURegs:$addr),
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(SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
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}
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let Predicates = [IsN64] in {
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def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
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def : Pat<(store_u FGR32:$src, CPU64Regs:$addr),
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(SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;
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}
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@ -310,7 +310,7 @@ class FFMADDSUB<bits<3> funct, bits<3> fmt, dag outs, dag ins, string asmstr,
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}
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// FP indexed load/store instructions.
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class FFMemIdx<bits<6> _funct, dag outs, dag ins, string asmstr,
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class FFMemIdx<bits<6> funct, dag outs, dag ins, string asmstr,
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list<dag> pattern> :
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MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
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{
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@ -318,7 +318,6 @@ class FFMemIdx<bits<6> _funct, dag outs, dag ins, string asmstr,
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bits<5> index;
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bits<5> fs;
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bits<5> fd;
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bits<6> funct;
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let Opcode = 0x13;
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@ -1,10 +1,14 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
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%struct.S = type <{ [4 x float] }>
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%struct.S2 = type <{ [4 x double] }>
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%struct.S3 = type <{ i8, float }>
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@s = external global [4 x %struct.S]
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@gf = external global float
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@gd = external global double
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@s2 = external global [4 x %struct.S2]
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@s3 = external global %struct.S3
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define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
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entry:
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@ -57,3 +61,38 @@ entry:
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ret void
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}
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define double @foo6(i32 %b, i32 %c) nounwind readonly {
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entry:
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; CHECK: foo6
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; CHECK-NOT: ldxc1
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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%0 = load double* %arrayidx1, align 1
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ret double %0
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}
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define void @foo7(i32 %b, i32 %c) nounwind {
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entry:
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; CHECK: foo7
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; CHECK-NOT: sdxc1
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%0 = load double* @gd, align 8
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%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
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store double %0, double* %arrayidx1, align 1
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ret void
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}
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define float @foo8() nounwind readonly {
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entry:
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; CHECK: foo8
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; CHECK: luxc1
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%0 = load float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
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ret float %0
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}
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define void @foo9(float %f) nounwind {
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entry:
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; CHECK: foo9
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; CHECK: suxc1
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store float %f, float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
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ret void
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}
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@ -1,10 +1,14 @@
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; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
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%struct.S = type <{ [4 x float] }>
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%struct.S2 = type <{ [4 x double] }>
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%struct.S3 = type <{ i8, float }>
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@s = external global [4 x %struct.S]
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@gf = external global float
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@gd = external global double
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@s2 = external global [4 x %struct.S2]
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@s3 = external global %struct.S3
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define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
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entry:
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@ -65,3 +69,42 @@ entry:
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ret void
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}
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define double @foo6(i32 %b, i32 %c) nounwind readonly {
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entry:
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; CHECK: foo6
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; CHECK-NOT: ldxc1
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%idxprom = zext i32 %c to i64
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%idxprom1 = zext i32 %b to i64
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%arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
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%0 = load double* %arrayidx2, align 1
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ret double %0
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}
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define void @foo7(i32 %b, i32 %c) nounwind {
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entry:
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; CHECK: foo7
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; CHECK-NOT: sdxc1
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%0 = load double* @gd, align 8
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%idxprom = zext i32 %c to i64
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%idxprom1 = zext i32 %b to i64
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%arrayidx2 = getelementptr inbounds [4 x %struct.S2]* @s2, i64 0, i64 %idxprom1, i32 0, i64 %idxprom
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store double %0, double* %arrayidx2, align 1
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ret void
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}
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define float @foo8() nounwind readonly {
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entry:
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; CHECK: foo8
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; CHECK: luxc1
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%0 = load float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1
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ret float %0
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}
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define void @foo9(float %f) nounwind {
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entry:
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; CHECK: foo9
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; CHECK: suxc1
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store float %f, float* getelementptr inbounds (%struct.S3* @s3, i64 0, i32 1), align 1
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ret void
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}
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