AMDGPU: Annotate call graph with used features
Previously this wouldn't detect used features indirectly used in callee functions. llvm-svn: 307967
This commit is contained in:
Matt Arsenault
parent
5b67cd3567
commit
6b93046f29
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@ -56,7 +56,7 @@ extern char &AMDGPUMachineCFGStructurizerID;
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void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
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ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
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Pass *createAMDGPUAnnotateKernelFeaturesPass();
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void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
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extern char &AMDGPUAnnotateKernelFeaturesID;
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@ -15,8 +15,10 @@
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Analysis/CallGraphSCCPass.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/InstIterator.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Module.h"
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@ -26,26 +28,30 @@ using namespace llvm;
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namespace {
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class AMDGPUAnnotateKernelFeatures : public ModulePass {
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class AMDGPUAnnotateKernelFeatures : public CallGraphSCCPass {
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private:
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const TargetMachine *TM = nullptr;
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AMDGPUAS AS;
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static bool hasAddrSpaceCast(const Function &F, AMDGPUAS AS);
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void addAttrToCallers(Function *Intrin, StringRef AttrName);
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bool addFeatureAttributes(Function &F);
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void addAttrToCallers(Function &Intrin, StringRef AttrName);
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bool addAttrsForIntrinsics(Module &M, ArrayRef<StringRef[2]>);
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public:
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static char ID;
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AMDGPUAnnotateKernelFeatures() : ModulePass(ID) {}
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bool runOnModule(Module &M) override;
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AMDGPUAnnotateKernelFeatures() : CallGraphSCCPass(ID) {}
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bool doInitialization(CallGraph &CG) override;
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bool runOnSCC(CallGraphSCC &SCC) override;
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StringRef getPassName() const override {
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return "AMDGPU Annotate Kernel Features";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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ModulePass::getAnalysisUsage(AU);
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CallGraphSCCPass::getAnalysisUsage(AU);
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}
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static bool visitConstantExpr(const ConstantExpr *CE, AMDGPUAS AS);
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@ -121,16 +127,108 @@ bool AMDGPUAnnotateKernelFeatures::visitConstantExprsRecursively(
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return false;
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}
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// Return true if an addrspacecast is used that requires the queue ptr.
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bool AMDGPUAnnotateKernelFeatures::hasAddrSpaceCast(const Function &F,
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AMDGPUAS AS) {
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// We do not need to note the x workitem or workgroup id because they are always
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// initialized.
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//
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// TODO: We should not add the attributes if the known compile time workgroup
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// size is 1 for y/z.
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static StringRef intrinsicToAttrName(Intrinsic::ID ID, bool &IsQueuePtr) {
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switch (ID) {
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case Intrinsic::amdgcn_workitem_id_y:
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case Intrinsic::r600_read_tidig_y:
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return "amdgpu-work-item-id-y";
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case Intrinsic::amdgcn_workitem_id_z:
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case Intrinsic::r600_read_tidig_z:
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return "amdgpu-work-item-id-z";
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case Intrinsic::amdgcn_workgroup_id_y:
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case Intrinsic::r600_read_tgid_y:
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return "amdgpu-work-group-id-y";
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case Intrinsic::amdgcn_workgroup_id_z:
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case Intrinsic::r600_read_tgid_z:
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return "amdgpu-work-group-id-z";
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case Intrinsic::amdgcn_dispatch_ptr:
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return "amdgpu-dispatch-ptr";
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case Intrinsic::amdgcn_dispatch_id:
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return "amdgpu-dispatch-id";
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case Intrinsic::amdgcn_queue_ptr:
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case Intrinsic::trap:
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case Intrinsic::debugtrap:
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IsQueuePtr = true;
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return "amdgpu-queue-ptr";
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default:
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return "";
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}
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}
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static bool handleAttr(Function &Parent, const Function &Callee,
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StringRef Name) {
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if (Callee.hasFnAttribute(Name)) {
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Parent.addFnAttr(Name);
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return true;
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}
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return false;
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}
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static void copyFeaturesToFunction(Function &Parent, const Function &Callee,
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bool &NeedQueuePtr) {
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static const StringRef AttrNames[] = {
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// .x omitted
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{ "amdgpu-work-item-id-y" },
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{ "amdgpu-work-item-id-z" },
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// .x omitted
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{ "amdgpu-work-group-id-y" },
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{ "amdgpu-work-group-id-z" },
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{ "amdgpu-dispatch-ptr" },
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{ "amdgpu-dispatch-id" }
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};
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if (handleAttr(Parent, Callee, "amdgpu-queue-ptr"))
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NeedQueuePtr = true;
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for (StringRef AttrName : AttrNames)
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handleAttr(Parent, Callee, AttrName);
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}
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bool AMDGPUAnnotateKernelFeatures::addFeatureAttributes(Function &F) {
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bool HasApertureRegs = TM->getSubtarget<AMDGPUSubtarget>(F).hasApertureRegs();
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SmallPtrSet<const Constant *, 8> ConstantExprVisited;
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for (const BasicBlock &BB : F) {
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for (const Instruction &I : BB) {
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bool Changed = false;
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bool NeedQueuePtr = false;
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for (BasicBlock &BB : F) {
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for (Instruction &I : BB) {
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CallSite CS(&I);
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if (CS) {
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Function *Callee = CS.getCalledFunction();
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// TODO: Do something with indirect calls.
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if (!Callee)
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continue;
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Intrinsic::ID IID = Callee->getIntrinsicID();
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if (IID == Intrinsic::not_intrinsic) {
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copyFeaturesToFunction(F, *Callee, NeedQueuePtr);
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Changed = true;
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} else {
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StringRef AttrName = intrinsicToAttrName(IID, NeedQueuePtr);
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if (!AttrName.empty()) {
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F.addFnAttr(AttrName);
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Changed = true;
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}
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}
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}
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if (NeedQueuePtr || HasApertureRegs)
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continue;
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if (const AddrSpaceCastInst *ASC = dyn_cast<AddrSpaceCastInst>(&I)) {
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if (castRequiresQueuePtr(ASC, AS))
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return true;
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if (castRequiresQueuePtr(ASC, AS)) {
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NeedQueuePtr = true;
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continue;
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}
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}
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for (const Use &U : I.operands()) {
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@ -138,20 +236,27 @@ bool AMDGPUAnnotateKernelFeatures::hasAddrSpaceCast(const Function &F,
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if (!OpC)
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continue;
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if (visitConstantExprsRecursively(OpC, ConstantExprVisited, AS))
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return true;
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if (visitConstantExprsRecursively(OpC, ConstantExprVisited, AS)) {
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NeedQueuePtr = true;
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break;
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}
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}
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}
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}
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return false;
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if (NeedQueuePtr) {
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F.addFnAttr("amdgpu-queue-ptr");
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Changed = true;
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}
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return Changed;
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}
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void AMDGPUAnnotateKernelFeatures::addAttrToCallers(Function *Intrin,
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void AMDGPUAnnotateKernelFeatures::addAttrToCallers(Function &Intrin,
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StringRef AttrName) {
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SmallPtrSet<Function *, 4> SeenFuncs;
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for (User *U : Intrin->users()) {
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for (User *U : Intrin.users()) {
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// CallInst is the only valid user for an intrinsic.
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CallInst *CI = cast<CallInst>(U);
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@ -168,7 +273,7 @@ bool AMDGPUAnnotateKernelFeatures::addAttrsForIntrinsics(
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for (const StringRef *Arr : IntrinsicToAttr) {
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if (Function *Fn = M.getFunction(Arr[0])) {
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addAttrToCallers(Fn, Arr[1]);
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addAttrToCallers(*Fn, Arr[1]);
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Changed = true;
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}
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}
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@ -176,62 +281,33 @@ bool AMDGPUAnnotateKernelFeatures::addAttrsForIntrinsics(
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return Changed;
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}
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bool AMDGPUAnnotateKernelFeatures::runOnModule(Module &M) {
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bool AMDGPUAnnotateKernelFeatures::runOnSCC(CallGraphSCC &SCC) {
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Module &M = SCC.getCallGraph().getModule();
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Triple TT(M.getTargetTriple());
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AS = AMDGPU::getAMDGPUAS(M);
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static const StringRef IntrinsicToAttr[][2] = {
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// .x omitted
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{ "llvm.amdgcn.workitem.id.y", "amdgpu-work-item-id-y" },
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{ "llvm.amdgcn.workitem.id.z", "amdgpu-work-item-id-z" },
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bool Changed = false;
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for (CallGraphNode *I : SCC) {
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Function *F = I->getFunction();
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if (!F || F->isDeclaration())
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continue;
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{ "llvm.amdgcn.workgroup.id.y", "amdgpu-work-group-id-y" },
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{ "llvm.amdgcn.workgroup.id.z", "amdgpu-work-group-id-z" },
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{ "llvm.r600.read.tgid.y", "amdgpu-work-group-id-y" },
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{ "llvm.r600.read.tgid.z", "amdgpu-work-group-id-z" },
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// .x omitted
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{ "llvm.r600.read.tidig.y", "amdgpu-work-item-id-y" },
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{ "llvm.r600.read.tidig.z", "amdgpu-work-item-id-z" }
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};
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static const StringRef HSAIntrinsicToAttr[][2] = {
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{ "llvm.amdgcn.dispatch.ptr", "amdgpu-dispatch-ptr" },
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{ "llvm.amdgcn.queue.ptr", "amdgpu-queue-ptr" },
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{ "llvm.amdgcn.dispatch.id", "amdgpu-dispatch-id" },
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{ "llvm.trap", "amdgpu-queue-ptr" },
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{ "llvm.debugtrap", "amdgpu-queue-ptr" }
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};
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// TODO: We should not add the attributes if the known compile time workgroup
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// size is 1 for y/z.
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// TODO: Intrinsics that require queue ptr.
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// We do not need to note the x workitem or workgroup id because they are
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// always initialized.
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bool Changed = addAttrsForIntrinsics(M, IntrinsicToAttr);
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if (TT.getOS() == Triple::AMDHSA || TT.getOS() == Triple::Mesa3D) {
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Changed |= addAttrsForIntrinsics(M, HSAIntrinsicToAttr);
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for (Function &F : M) {
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if (F.hasFnAttribute("amdgpu-queue-ptr"))
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continue;
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auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
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bool HasApertureRegs = TPC && TPC->getTM<TargetMachine>()
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.getSubtarget<AMDGPUSubtarget>(F)
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.hasApertureRegs();
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if (!HasApertureRegs && hasAddrSpaceCast(F, AS))
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F.addFnAttr("amdgpu-queue-ptr");
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}
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Changed |= addFeatureAttributes(*F);
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}
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return Changed;
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}
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ModulePass *llvm::createAMDGPUAnnotateKernelFeaturesPass() {
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bool AMDGPUAnnotateKernelFeatures::doInitialization(CallGraph &CG) {
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auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
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if (!TPC)
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report_fatal_error("TargetMachine is required");
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AS = AMDGPU::getAMDGPUAS(CG.getModule());
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TM = &TPC->getTM<TargetMachine>();
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return false;
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}
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Pass *llvm::createAMDGPUAnnotateKernelFeaturesPass() {
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return new AMDGPUAnnotateKernelFeatures();
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}
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@ -0,0 +1,200 @@
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; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s
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declare i32 @llvm.amdgcn.workgroup.id.y() #0
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declare i32 @llvm.amdgcn.workgroup.id.z() #0
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declare i32 @llvm.amdgcn.workitem.id.y() #0
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declare i32 @llvm.amdgcn.workitem.id.z() #0
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declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
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declare i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0
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declare i64 @llvm.amdgcn.dispatch.id() #0
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; HSA: define void @use_workitem_id_y() #1 {
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define void @use_workitem_id_y() #1 {
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%val = call i32 @llvm.amdgcn.workitem.id.y()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workitem_id_z() #2 {
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define void @use_workitem_id_z() #1 {
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%val = call i32 @llvm.amdgcn.workitem.id.z()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workgroup_id_y() #3 {
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define void @use_workgroup_id_y() #1 {
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%val = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workgroup_id_z() #4 {
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define void @use_workgroup_id_z() #1 {
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%val = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_dispatch_ptr() #5 {
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define void @use_dispatch_ptr() #1 {
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%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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store volatile i8 addrspace(2)* %dispatch.ptr, i8 addrspace(2)* addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_queue_ptr() #6 {
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define void @use_queue_ptr() #1 {
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%queue.ptr = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr()
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store volatile i8 addrspace(2)* %queue.ptr, i8 addrspace(2)* addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_dispatch_id() #7 {
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define void @use_dispatch_id() #1 {
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%val = call i64 @llvm.amdgcn.dispatch.id()
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store volatile i64 %val, i64 addrspace(1)* undef
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ret void
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}
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; HSA: define void @use_workgroup_id_y_workgroup_id_z() #8 {
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define void @use_workgroup_id_y_workgroup_id_z() #1 {
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%val0 = call i32 @llvm.amdgcn.workgroup.id.y()
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%val1 = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %val0, i32 addrspace(1)* undef
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store volatile i32 %val1, i32 addrspace(1)* undef
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ret void
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}
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; HSA: define void @func_indirect_use_workitem_id_y() #1 {
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define void @func_indirect_use_workitem_id_y() #1 {
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call void @use_workitem_id_y()
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ret void
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}
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; HSA: define void @func_indirect_use_workitem_id_z() #2 {
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define void @func_indirect_use_workitem_id_z() #1 {
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call void @use_workitem_id_z()
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ret void
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}
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; HSA: define void @func_indirect_use_workgroup_id_y() #3 {
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define void @func_indirect_use_workgroup_id_y() #1 {
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call void @use_workgroup_id_y()
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ret void
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}
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; HSA: define void @func_indirect_use_workgroup_id_z() #4 {
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define void @func_indirect_use_workgroup_id_z() #1 {
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call void @use_workgroup_id_z()
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ret void
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}
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; HSA: define void @func_indirect_indirect_use_workgroup_id_y() #3 {
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define void @func_indirect_indirect_use_workgroup_id_y() #1 {
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call void @func_indirect_use_workgroup_id_y()
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ret void
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}
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; HSA: define void @indirect_x2_use_workgroup_id_y() #3 {
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define void @indirect_x2_use_workgroup_id_y() #1 {
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call void @func_indirect_indirect_use_workgroup_id_y()
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ret void
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}
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; HSA: define void @func_indirect_use_dispatch_ptr() #5 {
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define void @func_indirect_use_dispatch_ptr() #1 {
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call void @use_dispatch_ptr()
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ret void
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}
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; HSA: define void @func_indirect_use_queue_ptr() #6 {
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define void @func_indirect_use_queue_ptr() #1 {
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call void @use_queue_ptr()
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ret void
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}
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; HSA: define void @func_indirect_use_dispatch_id() #7 {
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define void @func_indirect_use_dispatch_id() #1 {
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call void @use_dispatch_id()
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ret void
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}
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; HSA: define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #9 {
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define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #1 {
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call void @func_indirect_use_workgroup_id_y_workgroup_id_z()
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ret void
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}
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; HSA: define void @recursive_use_workitem_id_y() #1 {
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define void @recursive_use_workitem_id_y() #1 {
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%val = call i32 @llvm.amdgcn.workitem.id.y()
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store volatile i32 %val, i32 addrspace(1)* undef
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call void @recursive_use_workitem_id_y()
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ret void
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}
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; HSA: define void @call_recursive_use_workitem_id_y() #1 {
|
||||
define void @call_recursive_use_workitem_id_y() #1 {
|
||||
call void @recursive_use_workitem_id_y()
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #6 {
|
||||
define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
|
||||
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
|
||||
store volatile i32 0, i32 addrspace(4)* %stof
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #10 {
|
||||
define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 {
|
||||
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
|
||||
store volatile i32 0, i32 addrspace(4)* %stof
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #11 {
|
||||
define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 {
|
||||
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)*
|
||||
store volatile i32 0, i32 addrspace(4)* %stof
|
||||
call void @func_indirect_use_queue_ptr()
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast() #6 {
|
||||
define void @indirect_use_group_to_flat_addrspacecast() #1 {
|
||||
call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null)
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast_gfx9() #9 {
|
||||
define void @indirect_use_group_to_flat_addrspacecast_gfx9() #1 {
|
||||
call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null)
|
||||
ret void
|
||||
}
|
||||
|
||||
; HSA: define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #6 {
|
||||
define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #1 {
|
||||
call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null)
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind readnone speculatable }
|
||||
attributes #1 = { nounwind "target-cpu"="fiji" }
|
||||
attributes #2 = { nounwind "target-cpu"="gfx900" }
|
||||
|
||||
; HSA: attributes #0 = { nounwind readnone speculatable }
|
||||
; HSA: attributes #1 = { nounwind "amdgpu-work-item-id-y" "target-cpu"="fiji" }
|
||||
; HSA: attributes #2 = { nounwind "amdgpu-work-item-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #3 = { nounwind "amdgpu-work-group-id-y" "target-cpu"="fiji" }
|
||||
; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #5 = { nounwind "amdgpu-dispatch-ptr" "target-cpu"="fiji" }
|
||||
; HSA: attributes #6 = { nounwind "amdgpu-queue-ptr" "target-cpu"="fiji" }
|
||||
; HSA: attributes #7 = { nounwind "amdgpu-dispatch-id" "target-cpu"="fiji" }
|
||||
; HSA: attributes #8 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "target-cpu"="fiji" }
|
||||
; HSA: attributes #9 = { nounwind "target-cpu"="fiji" }
|
||||
; HSA: attributes #10 = { nounwind "target-cpu"="gfx900" }
|
||||
; HSA: attributes #11 = { nounwind "amdgpu-queue-ptr" "target-cpu"="gfx900" }
|
||||
Loading…
Reference in New Issue