Add instruction encodings / disassembly support for l4r instructions.
llvm-svn: 173501
This commit is contained in:
Richard Osborne
parent
69a040d3eb
commit
6b86eec819
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@ -180,6 +180,16 @@ static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -636,6 +646,45 @@ DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
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}
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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}
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return S;
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}
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static DecodeStatus
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DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3;
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unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
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}
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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}
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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@ -218,8 +218,29 @@ class _F0R<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{4-0} = opc{4-0};
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}
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class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FL4R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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bits<4> d;
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let Inst{31-27} = opc{5-1};
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let Inst{26-21} = 0b111111;
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let Inst{20} = opc{0};
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let Inst{19-16} = d;
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let Inst{15-11} = 0b11111;
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}
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// L4R with 4th operand as both a source and a destination.
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class _FL4RSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _FL4R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeL4RSrcDstInstruction";
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}
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// L4R with 1st and 4th operand as both a source and a destination.
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class _FL4RSrcDstSrcDst<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _FL4R<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeL4RSrcDstSrcDstInstruction";
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}
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class _FL5R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -463,25 +463,20 @@ def ST8_l3r : _FL3R<0b100011100, (outs),
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}
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// Four operand long
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let Constraints = "$src1 = $dst1,$src2 = $dst2" in {
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def MACCU_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
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GRRegs:$src4),
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"maccu $dst1, $dst2, $src3, $src4",
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[]>;
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let Constraints = "$e = $a,$f = $b" in {
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def MACCU_l4r : _FL4RSrcDstSrcDst<
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0b000001, (outs GRRegs:$a, GRRegs:$b),
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(ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>;
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def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
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GRRegs:$src4),
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"maccs $dst1, $dst2, $src3, $src4",
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[]>;
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def MACCS_l4r : _FL4RSrcDstSrcDst<
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0b000010, (outs GRRegs:$a, GRRegs:$b),
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(ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>;
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}
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let Constraints = "$src1 = $dst2" in
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def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
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"crc8 $dst2, $dst1, $src2, $src3",
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[]>;
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let Constraints = "$e = $b" in
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def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),
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(ins GRRegs:$e, GRRegs:$c, GRRegs:$d),
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"crc8 $b, $a, $c, $d", []>;
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// Five operand long
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@ -472,3 +472,14 @@
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# CHECK: lsub r1, r8, r7, r11, r5
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0xcf 0xfd 0x85 0x0f
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# l4r instructions
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# CHECK: crc8 r6, r3, r4, r11
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0x73 0xfd 0xe6 0x07
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# CHECK: maccs r11, r8, r2, r4
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0xf8 0xfa 0xe8 0x0f
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# CHECK: maccu r0, r2, r5, r8
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0x44 0xfd 0xf2 0x07
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