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LowerCall() should always do getCopyFromReg() to reference the stack pointer. 

Machine instruction selection is much happier when operands are in virtual
registers.

llvm-svn: 97012
This commit is contained in:
Jim Grosbach 2010-02-24 01:43:03 +00:00
parent 328a607490
commit 6ad4bcb0da
2 changed files with 2 additions and 6 deletions
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6
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -924,7 +924,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
// These operations are automatically eliminated by the prolog/epilog pass // These operations are automatically eliminated by the prolog/epilog pass
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
RegsToPassVector RegsToPass; RegsToPassVector RegsToPass;
SmallVector<SDValue, 8> MemOpChains; SmallVector<SDValue, 8> MemOpChains;
@ -973,8 +973,6 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
} else { } else {
assert(VA.isMemLoc()); assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
dl, DAG, VA, Flags)); dl, DAG, VA, Flags));
@ -987,8 +985,6 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
} else { } else {
assert(VA.isMemLoc()); assert(VA.isMemLoc());
if (StackPtr.getNode() == 0)
StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
dl, DAG, VA, Flags)); dl, DAG, VA, Flags));

2
llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll
View File

@ -52,7 +52,7 @@ bb420: ; preds = %bb20, %bb20
; CHECK: str r{{[0-7]}}, [sp] ; CHECK: str r{{[0-7]}}, [sp]
; CHECK: str r{{[0-7]}}, [sp, #+4] ; CHECK: str r{{[0-7]}}, [sp, #+4]
; CHECK: str r{{[0-7]}}, [sp, #+8] ; CHECK: str r{{[0-7]}}, [sp, #+8]
; CHECK: str r{{[0-7]}}, [sp, #+24] ; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #+24]
store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_hold, align 4
store %union.rec* null, %union.rec** @zz_res, align 4 store %union.rec* null, %union.rec** @zz_res, align 4
store %union.rec* %x, %union.rec** @zz_hold, align 4 store %union.rec* %x, %union.rec** @zz_hold, align 4