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Rename register classes to be upper case to make it obvious that they are X86 

specific in the tree patterns

llvm-svn: 7578
This commit is contained in:
Chris Lattner 2003-08-04 20:58:29 +00:00
parent ad9e792bef
commit 6aa90493a3
2 changed files with 8 additions and 8 deletions
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8
llvm/lib/Target/X86/X86RegisterInfo.cpp
View File

@ -254,14 +254,14 @@ X86RegisterInfo::getRegClassForType(const Type* Ty) const {
default: assert(0 && "Invalid type to getClass!");
case Type::BoolTyID:
case Type::SByteTyID:
case Type::UByteTyID: return &r8Instance;
case Type::UByteTyID: return &R8Instance;
case Type::ShortTyID:
case Type::UShortTyID: return &r16Instance;
case Type::UShortTyID: return &R16Instance;
case Type::IntTyID:
case Type::UIntTyID:
case Type::PointerTyID: return &r32Instance;
case Type::PointerTyID: return &R32Instance;
case Type::FloatTyID:
case Type::DoubleTyID: return &rFPInstance;
case Type::DoubleTyID: return &RFPInstance;
}
}

8
llvm/lib/Target/X86/X86RegisterInfo.td
View File

@ -69,8 +69,8 @@ def : RegisterAliases<SP, [ESP]>; def : RegisterAliases<BP, [EBP]>;
// top-level register classes. The order specified in the register list is
// implicitly defined to be the register allocation order.
//
def r8 : RegisterClass<i8, 1, [AL, CL, DL, BL, AH, CH, DH, BH]>;
def r16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
def R8 : RegisterClass<i8, 1, [AL, CL, DL, BL, AH, CH, DH, BH]>;
def R16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
@ -81,7 +81,7 @@ def r16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
}];
}
def r32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
def R32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
@ -92,7 +92,7 @@ def r32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
}];
}
def rFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
def RFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
// Registers which cannot be allocated... and are thus left unnamed.
def : RegisterClass<f80, 4, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]>;