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R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman 

We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184015
This commit is contained in:
Tom Stellard 2013-06-14 22:12:24 +00:00
parent d99b7932ae
commit 6aa0d5578d
3 changed files with 60 additions and 37 deletions
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1
llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp
View File

@ -370,6 +370,7 @@ public:
case AMDGPU::R600_ExportSwz:
case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
case AMDGPU::RAT_WRITE_CACHELESS_128_eg:
case AMDGPU::RAT_STORE_DWORD_cm:
DEBUG(dbgs() << CfCount << ":"; MI->dump(););
CfCount++;
break;

93
llvm/lib/Target/R600/R600Instructions.td
View File

@ -235,14 +235,26 @@ def TEX_SHADOW_ARRAY : PatLeaf<
}]
>;
class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, dag outs,
class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> mask, dag outs,
dag ins, string asm, list<dag> pattern> :
InstR600ISA <outs, ins, asm, pattern>,
CF_ALLOC_EXPORT_WORD0_RAT, CF_ALLOC_EXPORT_WORD1_BUF {
let cf_inst = cfinst;
let rat_id = 0;
let rat_inst = ratinst;
let rat_id = ratid;
let rim = 0;
// XXX: Have a separate instruction for non-indexed writes.
let type = 1;
let rw_rel = 0;
let elem_size = 0;
let array_size = 0;
let comp_mask = mask;
let burst_count = 0;
let vpm = 0;
let cf_inst = cfinst;
let mark = 0;
let barrier = 1;
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
@ -1210,6 +1222,33 @@ def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
def : SIN_PAT <SIN_eg>;
def : COS_PAT <COS_eg>;
def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
//===----------------------------------------------------------------------===//
// Memory read/write instructions
//===----------------------------------------------------------------------===//
let usesCustomInserter = 1 in {
class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> mask, string name,
list<dag> pattern>
: EG_CF_RAT <0x57, 0x2, mask, (outs), ins, name, pattern> {
}
} // End usesCustomInserter = 1
// 32-bit store
def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
(ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop",
[(global_store i32:$rw_gpr, i32:$index_gpr)]
>;
//128-bit store
def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
(ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop",
[(global_store v4i32:$rw_gpr, i32:$index_gpr)]
>;
} // End Predicates = [isEG]
//===----------------------------------------------------------------------===//
@ -1367,40 +1406,6 @@ let hasSideEffects = 1 in {
//===----------------------------------------------------------------------===//
// Memory read/write instructions
//===----------------------------------------------------------------------===//
let usesCustomInserter = 1 in {
class RAT_WRITE_CACHELESS_eg <dag ins, bits<4> mask, string name,
list<dag> pattern>
: EG_CF_RAT <0x57, 0x2, 0, (outs), ins, name, pattern> {
let rim = 0;
// XXX: Have a separate instruction for non-indexed writes.
let type = 1;
let rw_rel = 0;
let elem_size = 0;
let array_size = 0;
let comp_mask = mask;
let burst_count = 0;
let vpm = 0;
let mark = 0;
let barrier = 1;
}
} // End usesCustomInserter = 1
// 32-bit store
def RAT_WRITE_CACHELESS_32_eg : RAT_WRITE_CACHELESS_eg <
(ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
0x1, "RAT_WRITE_CACHELESS_32_eg $rw_gpr, $index_gpr, $eop",
[(global_store i32:$rw_gpr, i32:$index_gpr)]
>;
//128-bit store
def RAT_WRITE_CACHELESS_128_eg : RAT_WRITE_CACHELESS_eg <
(ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop),
0xf, "RAT_WRITE_CACHELESS_128 $rw_gpr.XYZW, $index_gpr, $eop",
[(global_store v4i32:$rw_gpr, i32:$index_gpr)]
>;
class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
: InstR600ISA <outs, (ins MEMxi:$ptr), name, pattern>,
@ -1575,6 +1580,10 @@ def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
defm R600_ : RegisterLoadStore <R600_Reg32, FRAMEri, ADDRIndirect>;
//===----------------------------------------------------------------------===//
// Cayman Instructions
//===----------------------------------------------------------------------===//
let Predicates = [isCayman] in {
let isVector = 1 in {
@ -1616,6 +1625,16 @@ def : Pat <
def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>;
def RAT_STORE_DWORD_cm : EG_CF_RAT <
0x57, 0x14, 0x1, (outs),
(ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
"EXPORT_RAT_INST_STORE_DWORD $rw_gpr, $index_gpr",
[(global_store i32:$rw_gpr, i32:$index_gpr)]
> {
let eop = 0; // This bit is not used on Cayman.
}
} // End isCayman
//===----------------------------------------------------------------------===//

3
llvm/test/CodeGen/R600/store.ll
View File

@ -1,9 +1,12 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
; floating-point store
; EG-CHECK: @store_f32
; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
; CM-CHECK: @store_f32
; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
; SI-CHECK: @store_f32
; SI-CHECK: BUFFER_STORE_DWORD