[X86] Don't use RCP14 and RSQRT14 for reciprocal estimations or for legacy SSE rcp/rsqrt intrinsics when AVX512 features are enabled.
Summary: AVX512 added RCP14 and RSQRT instructions which improve accuracy over the legacy RCP and RSQRT instruction, but not enough accuracy to remove the need for a Newton Raphson refinement. Currently we use these new instructions for the legacy packed SSE instrinics, but not the scalar instrinsics. And we use it for fast math optimization of division and reciprocal sqrt. I think switching the legacy instrinsics maybe surprising to the user since it changes the answer based on which processor you're using regardless of any fastmath settings. It's also weird that we did something different between scalar and packed. As far at the reciprocal estimation, I think it creates unnecessary deltas in our output behavior (and prevents EVEX->VEX). A little playing around with gcc and icc and godbolt suggest they don't change which instructions they use here. This patch adds new X86ISD nodes for the RCP14/RSQRT14 and uses those for the new intrinsics. Leaving the old intrinsics to use the old instructions. Going forward I think our focus should be on -Supporting 512-bit vectors, which will have to use the RCP14/RSQRT14. -Using RSQRT28/RCP28 to remove the Newton Raphson step on processors with AVX512ER -Supporting double precision. Reviewers: zvi, DavidKreitzer, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39583 llvm-svn: 317413
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@ -24808,9 +24808,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::FMAXC: return "X86ISD::FMAXC";
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case X86ISD::FMAXC: return "X86ISD::FMAXC";
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case X86ISD::FMINC: return "X86ISD::FMINC";
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case X86ISD::FMINC: return "X86ISD::FMINC";
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case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
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case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
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case X86ISD::FRSQRTS: return "X86ISD::FRSQRTS";
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case X86ISD::FRCP: return "X86ISD::FRCP";
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case X86ISD::FRCP: return "X86ISD::FRCP";
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case X86ISD::FRCPS: return "X86ISD::FRCPS";
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case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
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case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
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case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
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case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
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case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
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case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
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@ -24988,9 +24986,13 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::SELECT: return "X86ISD::SELECT";
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case X86ISD::SELECT: return "X86ISD::SELECT";
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case X86ISD::SELECTS: return "X86ISD::SELECTS";
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case X86ISD::SELECTS: return "X86ISD::SELECTS";
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case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
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case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
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case X86ISD::RCP14: return "X86ISD::RCP14";
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case X86ISD::RCP14S: return "X86ISD::RCP14S";
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case X86ISD::RCP28: return "X86ISD::RCP28";
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case X86ISD::RCP28: return "X86ISD::RCP28";
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case X86ISD::RCP28S: return "X86ISD::RCP28S";
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case X86ISD::RCP28S: return "X86ISD::RCP28S";
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case X86ISD::EXP2: return "X86ISD::EXP2";
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case X86ISD::EXP2: return "X86ISD::EXP2";
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case X86ISD::RSQRT14: return "X86ISD::RSQRT14";
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case X86ISD::RSQRT14S: return "X86ISD::RSQRT14S";
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case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
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case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
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case X86ISD::RSQRT28S: return "X86ISD::RSQRT28S";
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case X86ISD::RSQRT28S: return "X86ISD::RSQRT28S";
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case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
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case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
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@ -254,7 +254,9 @@ namespace llvm {
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/// Note that these typically require refinement
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/// Note that these typically require refinement
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/// in order to obtain suitable precision.
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/// in order to obtain suitable precision.
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FRSQRT, FRCP,
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FRSQRT, FRCP,
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FRSQRTS, FRCPS,
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// AVX-512 reciprocal approximations with a little more precision.
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RSQRT14, RSQRT14S, RCP14, RCP14S,
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// Thread Local Storage.
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// Thread Local Storage.
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TLSADDR,
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TLSADDR,
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@ -7362,13 +7362,13 @@ multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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}
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}
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}
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defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
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defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86rcp14s, f32x_info>,
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EVEX_CD8<32, CD8VT1>, T8PD, NotMemoryFoldable;
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EVEX_CD8<32, CD8VT1>, T8PD, NotMemoryFoldable;
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defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
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defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86rcp14s, f64x_info>,
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VEX_W, EVEX_CD8<64, CD8VT1>, T8PD, NotMemoryFoldable;
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VEX_W, EVEX_CD8<64, CD8VT1>, T8PD, NotMemoryFoldable;
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defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
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defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86rsqrt14s, f32x_info>,
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EVEX_CD8<32, CD8VT1>, T8PD, NotMemoryFoldable;
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EVEX_CD8<32, CD8VT1>, T8PD, NotMemoryFoldable;
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defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
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defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86rsqrt14s, f64x_info>,
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VEX_W, EVEX_CD8<64, CD8VT1>, T8PD, NotMemoryFoldable;
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VEX_W, EVEX_CD8<64, CD8VT1>, T8PD, NotMemoryFoldable;
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/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
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/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
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@ -7414,8 +7414,8 @@ multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
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}
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}
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}
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}
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defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
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defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86rsqrt14>;
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defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
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defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86rcp14>;
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/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
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/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
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multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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@ -56,8 +56,6 @@ def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>;
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def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp>;
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def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
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def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
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def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
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def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
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def X86frsqrt14s: SDNode<"X86ISD::FRSQRTS", SDTFPBinOp>;
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def X86frcp14s : SDNode<"X86ISD::FRCPS", SDTFPBinOp>;
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def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
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def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
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def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
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def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
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def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
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def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
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@ -498,10 +496,14 @@ def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
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def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>;
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def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>;
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def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>;
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def x86vpmadd52h : SDNode<"X86ISD::VPMADD52H", SDTIFma, [SDNPCommutative]>;
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def X86rsqrt14 : SDNode<"X86ISD::RSQRT14", SDTFPUnaryOp>;
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def X86rcp14 : SDNode<"X86ISD::RCP14", SDTFPUnaryOp>;
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def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOpRound>;
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def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", SDTFPUnaryOpRound>;
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def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOpRound>;
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def X86rcp28 : SDNode<"X86ISD::RCP28", SDTFPUnaryOpRound>;
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def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOpRound>;
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def X86exp2 : SDNode<"X86ISD::EXP2", SDTFPUnaryOpRound>;
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def X86rsqrt14s : SDNode<"X86ISD::RSQRT14S", SDTFPBinOp>;
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def X86rcp14s : SDNode<"X86ISD::RCP14S", SDTFPBinOp>;
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def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOpRound>;
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def X86rsqrt28s : SDNode<"X86ISD::RSQRT28S", SDTFPBinOpRound>;
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def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOpRound>;
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def X86rcp28s : SDNode<"X86ISD::RCP28S", SDTFPBinOpRound>;
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def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImmRound>;
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def X86RndScales : SDNode<"X86ISD::VRNDSCALES", SDTFPBinOpImmRound>;
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@ -3252,9 +3252,9 @@ defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
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// Reciprocal approximations. Note that these typically require refinement
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// Reciprocal approximations. Note that these typically require refinement
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// in order to obtain suitable precision.
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// in order to obtain suitable precision.
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defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
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defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
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sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS, [HasAVX, NoVLX] >;
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sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS, [HasAVX]>;
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defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
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defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
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sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP, [HasAVX, NoVLX]>;
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sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP, [HasAVX]>;
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// There is no f64 version of the reciprocal approximation instructions.
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// There is no f64 version of the reciprocal approximation instructions.
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@ -1428,26 +1428,26 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_ptestnm_w_128, CMP_MASK, X86ISD::TESTNM, 0),
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X86_INTRINSIC_DATA(avx512_ptestnm_w_128, CMP_MASK, X86ISD::TESTNM, 0),
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X86_INTRINSIC_DATA(avx512_ptestnm_w_256, CMP_MASK, X86ISD::TESTNM, 0),
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X86_INTRINSIC_DATA(avx512_ptestnm_w_256, CMP_MASK, X86ISD::TESTNM, 0),
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X86_INTRINSIC_DATA(avx512_ptestnm_w_512, CMP_MASK, X86ISD::TESTNM, 0),
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X86_INTRINSIC_DATA(avx512_ptestnm_w_512, CMP_MASK, X86ISD::TESTNM, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_pd_128, INTR_TYPE_1OP_MASK, X86ISD::FRCP, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_pd_128, INTR_TYPE_1OP_MASK, X86ISD::RCP14, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_pd_256, INTR_TYPE_1OP_MASK, X86ISD::FRCP, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_pd_256, INTR_TYPE_1OP_MASK, X86ISD::RCP14, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_pd_512, INTR_TYPE_1OP_MASK, X86ISD::FRCP, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_pd_512, INTR_TYPE_1OP_MASK, X86ISD::RCP14, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_ps_128, INTR_TYPE_1OP_MASK, X86ISD::FRCP, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_ps_128, INTR_TYPE_1OP_MASK, X86ISD::RCP14, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_ps_256, INTR_TYPE_1OP_MASK, X86ISD::FRCP, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_ps_256, INTR_TYPE_1OP_MASK, X86ISD::RCP14, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_ps_512, INTR_TYPE_1OP_MASK, X86ISD::FRCP, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_ps_512, INTR_TYPE_1OP_MASK, X86ISD::RCP14, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_sd, INTR_TYPE_SCALAR_MASK, X86ISD::FRCPS, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_sd, INTR_TYPE_SCALAR_MASK, X86ISD::RCP14S, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_ss, INTR_TYPE_SCALAR_MASK, X86ISD::FRCPS, 0),
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X86_INTRINSIC_DATA(avx512_rcp14_ss, INTR_TYPE_SCALAR_MASK, X86ISD::RCP14S, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_pd, INTR_TYPE_1OP_MASK_RM, X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_pd, INTR_TYPE_1OP_MASK_RM, X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ps, INTR_TYPE_1OP_MASK_RM, X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ps, INTR_TYPE_1OP_MASK_RM, X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_sd, INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28S, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_sd, INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28S, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ss, INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28S, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ss, INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28S, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_pd_128, INTR_TYPE_1OP_MASK, X86ISD::FRSQRT, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_pd_128, INTR_TYPE_1OP_MASK, X86ISD::RSQRT14, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_pd_256, INTR_TYPE_1OP_MASK, X86ISD::FRSQRT, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_pd_256, INTR_TYPE_1OP_MASK, X86ISD::RSQRT14, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_pd_512, INTR_TYPE_1OP_MASK, X86ISD::FRSQRT, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_pd_512, INTR_TYPE_1OP_MASK, X86ISD::RSQRT14, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_ps_128, INTR_TYPE_1OP_MASK, X86ISD::FRSQRT, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_ps_128, INTR_TYPE_1OP_MASK, X86ISD::RSQRT14, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_ps_256, INTR_TYPE_1OP_MASK, X86ISD::FRSQRT, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_ps_256, INTR_TYPE_1OP_MASK, X86ISD::RSQRT14, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_ps_512, INTR_TYPE_1OP_MASK, X86ISD::FRSQRT, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_ps_512, INTR_TYPE_1OP_MASK, X86ISD::RSQRT14, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_sd, INTR_TYPE_SCALAR_MASK, X86ISD::FRSQRTS, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_sd, INTR_TYPE_SCALAR_MASK, X86ISD::RSQRT14S, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_ss, INTR_TYPE_SCALAR_MASK, X86ISD::FRSQRTS, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt14_ss, INTR_TYPE_SCALAR_MASK, X86ISD::RSQRT14S, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_sd, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RSQRT28S, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_sd, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RSQRT28S, 0),
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@ -581,15 +581,10 @@ declare i32 @llvm.x86.avx.ptestz.256(<4 x i64>, <4 x i64>) nounwind readnone
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define <8 x float> @test_x86_avx_rcp_ps_256(<8 x float> %a0) {
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define <8 x float> @test_x86_avx_rcp_ps_256(<8 x float> %a0) {
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; AVX-LABEL: test_x86_avx_rcp_ps_256:
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; CHECK-LABEL: test_x86_avx_rcp_ps_256:
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; AVX: # BB#0:
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; CHECK: # BB#0:
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; AVX-NEXT: vrcpps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x53,0xc0]
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; CHECK-NEXT: vrcpps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x53,0xc0]
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; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
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; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_avx_rcp_ps_256:
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; AVX512VL: # BB#0:
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|
||||||
; AVX512VL-NEXT: vrcp14ps %ymm0, %ymm0 # encoding: [0x62,0xf2,0x7d,0x28,0x4c,0xc0]
|
|
||||||
; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
|
||||||
%res = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
|
%res = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
|
||||||
ret <8 x float> %res
|
ret <8 x float> %res
|
||||||
}
|
}
|
||||||
|
@ -619,15 +614,10 @@ declare <8 x float> @llvm.x86.avx.round.ps.256(<8 x float>, i32) nounwind readno
|
||||||
|
|
||||||
|
|
||||||
define <8 x float> @test_x86_avx_rsqrt_ps_256(<8 x float> %a0) {
|
define <8 x float> @test_x86_avx_rsqrt_ps_256(<8 x float> %a0) {
|
||||||
; AVX-LABEL: test_x86_avx_rsqrt_ps_256:
|
; CHECK-LABEL: test_x86_avx_rsqrt_ps_256:
|
||||||
; AVX: # BB#0:
|
; CHECK: # BB#0:
|
||||||
; AVX-NEXT: vrsqrtps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x52,0xc0]
|
; CHECK-NEXT: vrsqrtps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x52,0xc0]
|
||||||
; AVX-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
||||||
;
|
|
||||||
; AVX512VL-LABEL: test_x86_avx_rsqrt_ps_256:
|
|
||||||
; AVX512VL: # BB#0:
|
|
||||||
; AVX512VL-NEXT: vrsqrt14ps %ymm0, %ymm0 # encoding: [0x62,0xf2,0x7d,0x28,0x4e,0xc0]
|
|
||||||
; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
|
|
||||||
%res = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
|
%res = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
|
||||||
ret <8 x float> %res
|
ret <8 x float> %res
|
||||||
}
|
}
|
||||||
|
|
|
@ -3982,8 +3982,8 @@ define <8 x float> @test_rcpps(<8 x float> %a0, <8 x float> *%a1) {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: test_rcpps:
|
; SKX-LABEL: test_rcpps:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %ymm0, %ymm0 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %ymm0, %ymm0 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vrcp14ps (%rdi), %ymm1 # sched: [11:1.00]
|
; SKX-NEXT: vrcpps (%rdi), %ymm1 # sched: [11:1.00]
|
||||||
; SKX-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
|
; SKX-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: retq # sched: [7:1.00]
|
; SKX-NEXT: retq # sched: [7:1.00]
|
||||||
;
|
;
|
||||||
|
@ -4174,8 +4174,8 @@ define <8 x float> @test_rsqrtps(<8 x float> %a0, <8 x float> *%a1) {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: test_rsqrtps:
|
; SKX-LABEL: test_rsqrtps:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrsqrt14ps %ymm0, %ymm0 # sched: [4:1.00]
|
; SKX-NEXT: vrsqrtps %ymm0, %ymm0 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vrsqrt14ps (%rdi), %ymm1 # sched: [11:1.00]
|
; SKX-NEXT: vrsqrtps (%rdi), %ymm1 # sched: [11:1.00]
|
||||||
; SKX-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
|
; SKX-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: retq # sched: [7:1.00]
|
; SKX-NEXT: retq # sched: [7:1.00]
|
||||||
;
|
;
|
||||||
|
|
|
@ -416,7 +416,7 @@ define <4 x float> @v4f32_one_step(<4 x float> %x) #1 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v4f32_one_step:
|
; SKX-LABEL: v4f32_one_step:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %xmm0, %xmm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %xmm0, %xmm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0 # sched: [10:0.50]
|
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0 # sched: [10:0.50]
|
||||||
; SKX-NEXT: vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.33]
|
; SKX-NEXT: vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: retq # sched: [7:1.00]
|
; SKX-NEXT: retq # sched: [7:1.00]
|
||||||
|
@ -533,7 +533,7 @@ define <4 x float> @v4f32_two_step(<4 x float> %x) #2 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v4f32_two_step:
|
; SKX-LABEL: v4f32_two_step:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %xmm0, %xmm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %xmm0, %xmm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vbroadcastss {{.*#+}} xmm2 = [1,1,1,1] sched: [6:0.50]
|
; SKX-NEXT: vbroadcastss {{.*#+}} xmm2 = [1,1,1,1] sched: [6:0.50]
|
||||||
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:1.00]
|
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [4:0.33]
|
; SKX-NEXT: vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [4:0.33]
|
||||||
|
@ -691,7 +691,7 @@ define <8 x float> @v8f32_one_step(<8 x float> %x) #1 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v8f32_one_step:
|
; SKX-LABEL: v8f32_one_step:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %ymm0, %ymm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %ymm0, %ymm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0 # sched: [11:0.50]
|
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0 # sched: [11:0.50]
|
||||||
; SKX-NEXT: vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.33]
|
; SKX-NEXT: vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: retq # sched: [7:1.00]
|
; SKX-NEXT: retq # sched: [7:1.00]
|
||||||
|
@ -821,7 +821,7 @@ define <8 x float> @v8f32_two_step(<8 x float> %x) #2 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v8f32_two_step:
|
; SKX-LABEL: v8f32_two_step:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %ymm0, %ymm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %ymm0, %ymm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vbroadcastss {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
|
; SKX-NEXT: vbroadcastss {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
|
||||||
; SKX-NEXT: vmovaps %ymm1, %ymm3 # sched: [1:1.00]
|
; SKX-NEXT: vmovaps %ymm1, %ymm3 # sched: [1:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [4:0.33]
|
; SKX-NEXT: vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [4:0.33]
|
||||||
|
|
|
@ -478,7 +478,7 @@ define <4 x float> @v4f32_one_step2(<4 x float> %x) #1 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v4f32_one_step2:
|
; SKX-LABEL: v4f32_one_step2:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %xmm0, %xmm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %xmm0, %xmm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0 # sched: [10:0.50]
|
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0 # sched: [10:0.50]
|
||||||
; SKX-NEXT: vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.33]
|
; SKX-NEXT: vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm0 # sched: [10:0.50]
|
; SKX-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm0 # sched: [10:0.50]
|
||||||
|
@ -580,7 +580,7 @@ define <4 x float> @v4f32_one_step_2_divs(<4 x float> %x) #1 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v4f32_one_step_2_divs:
|
; SKX-LABEL: v4f32_one_step_2_divs:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %xmm0, %xmm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %xmm0, %xmm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0 # sched: [10:0.50]
|
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to4}, %xmm1, %xmm0 # sched: [10:0.50]
|
||||||
; SKX-NEXT: vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.33]
|
; SKX-NEXT: vfmadd132ps %xmm1, %xmm1, %xmm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1 # sched: [10:0.50]
|
; SKX-NEXT: vmulps {{.*}}(%rip), %xmm0, %xmm1 # sched: [10:0.50]
|
||||||
|
@ -708,7 +708,7 @@ define <4 x float> @v4f32_two_step2(<4 x float> %x) #2 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v4f32_two_step2:
|
; SKX-LABEL: v4f32_two_step2:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %xmm0, %xmm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %xmm0, %xmm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vbroadcastss {{.*#+}} xmm2 = [1,1,1,1] sched: [6:0.50]
|
; SKX-NEXT: vbroadcastss {{.*#+}} xmm2 = [1,1,1,1] sched: [6:0.50]
|
||||||
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:1.00]
|
; SKX-NEXT: vmovaps %xmm1, %xmm3 # sched: [1:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [4:0.33]
|
; SKX-NEXT: vfnmadd213ps %xmm2, %xmm0, %xmm3 # sched: [4:0.33]
|
||||||
|
@ -814,7 +814,7 @@ define <8 x float> @v8f32_one_step2(<8 x float> %x) #1 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v8f32_one_step2:
|
; SKX-LABEL: v8f32_one_step2:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %ymm0, %ymm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %ymm0, %ymm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0 # sched: [11:0.50]
|
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0 # sched: [11:0.50]
|
||||||
; SKX-NEXT: vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.33]
|
; SKX-NEXT: vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [11:0.50]
|
; SKX-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [11:0.50]
|
||||||
|
@ -925,7 +925,7 @@ define <8 x float> @v8f32_one_step_2_divs(<8 x float> %x) #1 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v8f32_one_step_2_divs:
|
; SKX-LABEL: v8f32_one_step_2_divs:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %ymm0, %ymm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %ymm0, %ymm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0 # sched: [11:0.50]
|
; SKX-NEXT: vfnmadd213ps {{.*}}(%rip){1to8}, %ymm1, %ymm0 # sched: [11:0.50]
|
||||||
; SKX-NEXT: vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.33]
|
; SKX-NEXT: vfmadd132ps %ymm1, %ymm1, %ymm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1 # sched: [11:0.50]
|
; SKX-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm1 # sched: [11:0.50]
|
||||||
|
@ -1067,7 +1067,7 @@ define <8 x float> @v8f32_two_step2(<8 x float> %x) #2 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v8f32_two_step2:
|
; SKX-LABEL: v8f32_two_step2:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %ymm0, %ymm1 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %ymm0, %ymm1 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vbroadcastss {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
|
; SKX-NEXT: vbroadcastss {{.*#+}} ymm2 = [1,1,1,1,1,1,1,1] sched: [7:0.50]
|
||||||
; SKX-NEXT: vmovaps %ymm1, %ymm3 # sched: [1:1.00]
|
; SKX-NEXT: vmovaps %ymm1, %ymm3 # sched: [1:1.00]
|
||||||
; SKX-NEXT: vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [4:0.33]
|
; SKX-NEXT: vfnmadd213ps %ymm2, %ymm0, %ymm3 # sched: [4:0.33]
|
||||||
|
@ -1124,7 +1124,7 @@ define <8 x float> @v8f32_no_step(<8 x float> %x) #3 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v8f32_no_step:
|
; SKX-LABEL: v8f32_no_step:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %ymm0, %ymm0 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %ymm0, %ymm0 # sched: [4:1.00]
|
||||||
; SKX-NEXT: retq # sched: [7:1.00]
|
; SKX-NEXT: retq # sched: [7:1.00]
|
||||||
%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
|
%div = fdiv fast <8 x float> <float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0, float 1.0>, %x
|
||||||
ret <8 x float> %div
|
ret <8 x float> %div
|
||||||
|
@ -1183,7 +1183,7 @@ define <8 x float> @v8f32_no_step2(<8 x float> %x) #3 {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: v8f32_no_step2:
|
; SKX-LABEL: v8f32_no_step2:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %ymm0, %ymm0 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %ymm0, %ymm0 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [11:0.50]
|
; SKX-NEXT: vmulps {{.*}}(%rip), %ymm0, %ymm0 # sched: [11:0.50]
|
||||||
; SKX-NEXT: retq # sched: [7:1.00]
|
; SKX-NEXT: retq # sched: [7:1.00]
|
||||||
%div = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %x
|
%div = fdiv fast <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, %x
|
||||||
|
|
|
@ -401,15 +401,10 @@ define <4 x float> @test_x86_sse_rcp_ps(<4 x float> %a0) {
|
||||||
; SSE-NEXT: rcpps %xmm0, %xmm0 ## encoding: [0x0f,0x53,0xc0]
|
; SSE-NEXT: rcpps %xmm0, %xmm0 ## encoding: [0x0f,0x53,0xc0]
|
||||||
; SSE-NEXT: retl ## encoding: [0xc3]
|
; SSE-NEXT: retl ## encoding: [0xc3]
|
||||||
;
|
;
|
||||||
; AVX2-LABEL: test_x86_sse_rcp_ps:
|
; VCHECK-LABEL: test_x86_sse_rcp_ps:
|
||||||
; AVX2: ## BB#0:
|
; VCHECK: ## BB#0:
|
||||||
; AVX2-NEXT: vrcpps %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x53,0xc0]
|
; VCHECK-NEXT: vrcpps %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x53,0xc0]
|
||||||
; AVX2-NEXT: retl ## encoding: [0xc3]
|
; VCHECK-NEXT: retl ## encoding: [0xc3]
|
||||||
;
|
|
||||||
; SKX-LABEL: test_x86_sse_rcp_ps:
|
|
||||||
; SKX: ## BB#0:
|
|
||||||
; SKX-NEXT: vrcp14ps %xmm0, %xmm0 ## encoding: [0x62,0xf2,0x7d,0x08,0x4c,0xc0]
|
|
||||||
; SKX-NEXT: retl ## encoding: [0xc3]
|
|
||||||
%res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
|
%res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
|
||||||
ret <4 x float> %res
|
ret <4 x float> %res
|
||||||
}
|
}
|
||||||
|
@ -438,15 +433,10 @@ define <4 x float> @test_x86_sse_rsqrt_ps(<4 x float> %a0) {
|
||||||
; SSE-NEXT: rsqrtps %xmm0, %xmm0 ## encoding: [0x0f,0x52,0xc0]
|
; SSE-NEXT: rsqrtps %xmm0, %xmm0 ## encoding: [0x0f,0x52,0xc0]
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||||||
; SSE-NEXT: retl ## encoding: [0xc3]
|
; SSE-NEXT: retl ## encoding: [0xc3]
|
||||||
;
|
;
|
||||||
; AVX2-LABEL: test_x86_sse_rsqrt_ps:
|
; VCHECK-LABEL: test_x86_sse_rsqrt_ps:
|
||||||
; AVX2: ## BB#0:
|
; VCHECK: ## BB#0:
|
||||||
; AVX2-NEXT: vrsqrtps %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x52,0xc0]
|
; VCHECK-NEXT: vrsqrtps %xmm0, %xmm0 ## encoding: [0xc5,0xf8,0x52,0xc0]
|
||||||
; AVX2-NEXT: retl ## encoding: [0xc3]
|
; VCHECK-NEXT: retl ## encoding: [0xc3]
|
||||||
;
|
|
||||||
; SKX-LABEL: test_x86_sse_rsqrt_ps:
|
|
||||||
; SKX: ## BB#0:
|
|
||||||
; SKX-NEXT: vrsqrt14ps %xmm0, %xmm0 ## encoding: [0x62,0xf2,0x7d,0x08,0x4e,0xc0]
|
|
||||||
; SKX-NEXT: retl ## encoding: [0xc3]
|
|
||||||
%res = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
|
%res = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1]
|
||||||
ret <4 x float> %res
|
ret <4 x float> %res
|
||||||
}
|
}
|
||||||
|
|
|
@ -2547,8 +2547,8 @@ define <4 x float> @test_rcpps(<4 x float> %a0, <4 x float> *%a1) {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: test_rcpps:
|
; SKX-LABEL: test_rcpps:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrcp14ps %xmm0, %xmm0 # sched: [4:1.00]
|
; SKX-NEXT: vrcpps %xmm0, %xmm0 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vrcp14ps (%rdi), %xmm1 # sched: [10:1.00]
|
; SKX-NEXT: vrcpps (%rdi), %xmm1 # sched: [10:1.00]
|
||||||
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
|
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: retq # sched: [7:1.00]
|
; SKX-NEXT: retq # sched: [7:1.00]
|
||||||
;
|
;
|
||||||
|
@ -2719,8 +2719,8 @@ define <4 x float> @test_rsqrtps(<4 x float> %a0, <4 x float> *%a1) {
|
||||||
;
|
;
|
||||||
; SKX-LABEL: test_rsqrtps:
|
; SKX-LABEL: test_rsqrtps:
|
||||||
; SKX: # BB#0:
|
; SKX: # BB#0:
|
||||||
; SKX-NEXT: vrsqrt14ps %xmm0, %xmm0 # sched: [4:1.00]
|
; SKX-NEXT: vrsqrtps %xmm0, %xmm0 # sched: [4:1.00]
|
||||||
; SKX-NEXT: vrsqrt14ps (%rdi), %xmm1 # sched: [10:1.00]
|
; SKX-NEXT: vrsqrtps (%rdi), %xmm1 # sched: [10:1.00]
|
||||||
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
|
; SKX-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [4:0.33]
|
||||||
; SKX-NEXT: retq # sched: [7:1.00]
|
; SKX-NEXT: retq # sched: [7:1.00]
|
||||||
;
|
;
|
||||||
|
|
Loading…
Reference in New Issue