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[AVX] Add TableGen classes for vector/subvector type constraints. 

This will be used to check patterns referencing a forthcoming
INSERT_SUBVECTOR SDNode and will also be used to check
EXTRACT_SUBVECTOR nodes.

llvm-svn: 124191
This commit is contained in:
David Greene 2011-01-25 16:16:32 +00:00
parent 912e161ce0
commit 672a4a297e
1 changed files with 14 additions and 0 deletions
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14
llvm/include/llvm/Target/TargetSelectionDAG.td
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@ -61,6 +61,13 @@ class SDTCisEltOfVec<int ThisOp, int OtherOp>
int OtherOpNum = OtherOp;
}
/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
/// with length less that of OtherOp, which is a vector type.
class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
: SDTypeConstraint<ThisOp> {
int OtherOpNum = OtherOp;
}
//===----------------------------------------------------------------------===//
// Selection DAG Type Profile definitions.
//
@ -183,6 +190,13 @@ def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
]>;
def SDTSubVecExtract : SDTypeProfile<1, 1, [// subvector extract
SDTCisSubVecOfVec<0,1>
]>;
def SDTSubVecInsert : SDTypeProfile<1, 2, [ // subvector insert
SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>
]>;
def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch
SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
]>;