replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Can't commute shufps. The high / low parts elements come from different vectors. 

llvm-svn: 29275
This commit is contained in:
Evan Cheng 2006-07-25 20:25:40 +00:00
parent 8902fd702b
commit 66ed41cac1
2 changed files with 1 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -207,24 +207,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
/// ///
MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
case X86::SHUFPSrri: { // A = SHUFPSrri B,C, M -> A = SHUFPSrri C,B, rotl(M,4)
unsigned A = MI->getOperand(0).getReg();
unsigned B = MI->getOperand(1).getReg();
unsigned C = MI->getOperand(2).getReg();
unsigned M = MI->getOperand(3).getImmedValue();
if (B == C) return 0;
return BuildMI(X86::SHUFPSrri, 3, A).addReg(C).addReg(B).
addImm(((M & 0xF) << 4) | ((M & 0xF0) >> 4));
}
case X86::SHUFPDrri: { // A = SHUFPDrri B,C, M -> A = SHUFPDrri C,B, rotl(M,1)
unsigned A = MI->getOperand(0).getReg();
unsigned B = MI->getOperand(1).getReg();
unsigned C = MI->getOperand(2).getReg();
unsigned M = MI->getOperand(3).getImmedValue();
if (B == C) return 0;
return BuildMI(X86::SHUFPDrri, 3, A).addReg(C).addReg(B).
addImm(((M & 0x1) << 1) | ((M & 0x2) >> 1));
}
case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)

3
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -1223,7 +1223,7 @@ def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
// Shuffle and unpack instructions // Shuffle and unpack instructions
let isTwoAddress = 1 in { let isTwoAddress = 1 in {
let isCommutable = 1, isConvertibleToThreeAddress = 1 in // Convert to pshufd let isConvertibleToThreeAddress = 1 in // Convert to pshufd
def SHUFPSrri : PSIi8<0xC6, MRMSrcReg, def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3), (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
"shufps {$src3, $src2, $dst|$dst, $src2, $src3}", "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
@ -1236,7 +1236,6 @@ def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
[(set VR128:$dst, (v4f32 (vector_shuffle [(set VR128:$dst, (v4f32 (vector_shuffle
VR128:$src1, (load addr:$src2), VR128:$src1, (load addr:$src2),
SHUFP_shuffle_mask:$src3)))]>; SHUFP_shuffle_mask:$src3)))]>;
let isCommutable = 1 in
def SHUFPDrri : PDIi8<0xC6, MRMSrcReg, def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3), (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
"shufpd {$src3, $src2, $dst|$dst, $src2, $src3}", "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",