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Remove fake instruction 'subc' (mnemonic for subfc). 

More pattern isel updates

llvm-svn: 20902
This commit is contained in:
Nate Begeman 2005-03-28 22:28:37 +00:00
parent 32e08b7c06
commit 66acad746f
3 changed files with 42 additions and 12 deletions
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50
llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
View File

@ -137,13 +137,22 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
if (GPR_remaining > 1) {
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
SDOperand root = DAG.getRoot();
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
root, DAG.getConstant(1, MVT::i32));
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
root, DAG.getConstant(0, MVT::i32));
// Create the pair of virtual registers
MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
unsigned virtReg =
MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
// FIXME: is this correct?
argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
argt = DAG.getCopyFromReg(virtReg+1, MVT::i32, newroot);
// Push the arguments for emitting into BB later
unsigned virtReg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
// Copy the extracted halves into the virtual registers
SDOperand argHi = DAG.getCopyFromReg(virtReg, MVT::i32, Hi);
SDOperand argLo = DAG.getCopyFromReg(virtReg+1, MVT::i32, Lo);
// Build the outgoing arg thingy
argt = newroot = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
argVR.push_back(virtReg); argVR.push_back(virtReg+1);
argPR.push_back(GPR[GPR_idx]); argPR.push_back(GPR[GPR_idx+1]);
argOp.push_back(PPC::OR); argOp.push_back(PPC::OR);
@ -592,6 +601,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
}
case ISD::ConstantFP:
assert(0 && "ISD::ConstantFP Unimplemented");
abort();
case ISD::MUL:
@ -688,14 +698,20 @@ unsigned ISel::SelectExpr(SDOperand N) {
return Result;
case ISD::ConstantPool:
abort();
Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
Tmp2 = MakeReg(MVT::i32);
BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
.addConstantPoolIndex(Tmp1);
BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
return Result;
case ISD::FrameIndex:
assert(0 && "ISD::FrameIndex Unimplemented");
abort();
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
unsigned Tmp1 = MakeReg(MVT::i32);
Tmp1 = MakeReg(MVT::i32);
BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
.addGlobalAddress(GV);
if (GV->hasWeakLinkage() || GV->isExternal()) {
@ -990,7 +1006,23 @@ unsigned ISel::SelectExpr(SDOperand N) {
return Result;
case ISD::ADD_PARTS:
case ISD::SUB_PARTS:
case ISD::SUB_PARTS: {
assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
"Not an i64 add/sub!");
// Emit all of the operands.
std::vector<unsigned> InVals;
for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
InVals.push_back(SelectExpr(N.getOperand(i)));
if (N.getOpcode() == ISD::ADD_PARTS) {
BuildMI(BB, PPC::ADDC, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
BuildMI(BB, PPC::ADDE, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
} else {
BuildMI(BB, PPC::SUBFC, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
BuildMI(BB, PPC::SUBFE, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
}
return Result+N.ResNo;
}
case ISD::UREM:
case ISD::SREM:
case ISD::SDIV:

2
llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
View File

@ -2392,7 +2392,7 @@ void PPC32ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
};
static const unsigned LongOpTab[2][5] = {
{ PPC::ADDC, PPC::SUBC, PPC::AND, PPC::OR, PPC::XOR },
{ PPC::ADDC, PPC::SUBFC, PPC::AND, PPC::OR, PPC::XOR },
{ PPC::ADDE, PPC::SUBFE, PPC::AND, PPC::OR, PPC::XOR }
};

2
llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
View File

@ -376,8 +376,6 @@ def SUBFE : XOForm_1<31, 136, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"subfe $rT, $rA, $rB">;
def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"sub $rT, $rA, $rB">;
def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"subc $rT, $rA, $rB">;
def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
"addme $rT, $rA">;
def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),