AVX-512: MUL operation lowering for v8i64
llvm-svn: 193083
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@ -12402,8 +12402,8 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
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return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
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}
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assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
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"Only know how to lower V2I64/V4I64 multiply");
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assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
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"Only know how to lower V2I64/V4I64/V8I64 multiply");
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// Ahi = psrlqi(a, 32);
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// Bhi = psrlqi(b, 32);
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@ -12422,7 +12422,8 @@ static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
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SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
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// Bit cast to 32-bit vectors for MULUDQ
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EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
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EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
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(VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
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A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
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B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
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Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
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@ -74,6 +74,15 @@ entry:
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ret <16 x float> %sub.i
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}
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; CHECK-LABEL: imulq512
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; CHECK: vpmuludq
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; CHECK: vpmuludq
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; CHECK: ret
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define <8 x i64> @imulq512(<8 x i64> %y, <8 x i64> %x) {
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%z = mul <8 x i64>%x, %y
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ret <8 x i64>%z
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}
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; CHECK-LABEL: mulpd512
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; CHECK: vmulpd
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; CHECK: ret
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@ -259,4 +268,4 @@ entry:
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%c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
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%d = and <8 x i64> %p1, %c
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ret <8 x i64>%d
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}
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}
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