For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64.
llvm-svn: 196456
This commit is contained in:
Jiangning Liu
parent
06bd7e64b9
commit
65d8e3422a
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@ -66,7 +66,7 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v1f32, &AArch64::FPR32RegClass);
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addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v2i32, &AArch64::FPR64RegClass);
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addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
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@ -409,6 +409,29 @@ static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
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StrOpc = StoreOps[Log2_32(Size)];
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}
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// FIXME: AArch64::DTripleRegClass and AArch64::QTripleRegClass don't really
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// have value type mapped, and they are both being defined as MVT::untyped.
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// Without knowing the MVT type, MachineLICM::getRegisterClassIDAndCost
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// would fail to figure out the register pressure correctly.
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std::pair<const TargetRegisterClass*, uint8_t>
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AArch64TargetLowering::findRepresentativeClass(MVT VT) const{
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const TargetRegisterClass *RRC = 0;
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uint8_t Cost = 1;
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switch (VT.SimpleTy) {
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default:
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return TargetLowering::findRepresentativeClass(VT);
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case MVT::v4i64:
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RRC = &AArch64::QPairRegClass;
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Cost = 2;
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break;
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case MVT::v8i64:
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RRC = &AArch64::QQuadRegClass;
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Cost = 4;
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break;
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}
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return std::make_pair(RRC, Cost);
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}
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MachineBasicBlock *
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AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Size,
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@ -343,6 +343,10 @@ public:
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virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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unsigned Intrinsic) const LLVM_OVERRIDE;
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protected:
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(MVT VT) const;
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private:
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const InstrItineraryData *Itins;
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@ -0,0 +1,164 @@
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; RUN: llc < %s -O2 -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define void @test_ldstq_4v(i8* noalias %io, i32 %count) {
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; CHECK-LABEL: test_ldstq_4v
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; CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
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; CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
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entry:
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%tobool62 = icmp eq i32 %count, 0
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br i1 %tobool62, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%count.addr.063 = phi i32 [ %dec, %while.body ], [ %count, %entry ]
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%dec = add i32 %count.addr.063, -1
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%vld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8(i8* %io, i32 1)
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%vld4.fca.0.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld4, 0
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%vld4.fca.1.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld4, 1
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%vld4.fca.2.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld4, 2
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%vld4.fca.3.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld4, 3
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tail call void @llvm.arm.neon.vst4.v16i8(i8* %io, <16 x i8> %vld4.fca.0.extract, <16 x i8> %vld4.fca.1.extract, <16 x i8> %vld4.fca.2.extract, <16 x i8> %vld4.fca.3.extract, i32 1)
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8(i8*, i32)
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declare void @llvm.arm.neon.vst4.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32)
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define void @test_ldstq_3v(i8* noalias %io, i32 %count) {
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; CHECK-LABEL: test_ldstq_3v
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; CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0]
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; CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0]
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entry:
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%tobool47 = icmp eq i32 %count, 0
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br i1 %tobool47, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%count.addr.048 = phi i32 [ %dec, %while.body ], [ %count, %entry ]
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%dec = add i32 %count.addr.048, -1
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%vld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %io, i32 1)
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%vld3.fca.0.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vld3, 0
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%vld3.fca.1.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vld3, 1
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%vld3.fca.2.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vld3, 2
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tail call void @llvm.arm.neon.vst3.v16i8(i8* %io, <16 x i8> %vld3.fca.0.extract, <16 x i8> %vld3.fca.1.extract, <16 x i8> %vld3.fca.2.extract, i32 1)
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8*, i32)
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declare void @llvm.arm.neon.vst3.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, i32)
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define void @test_ldstq_2v(i8* noalias %io, i32 %count) {
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; CHECK-LABEL: test_ldstq_2v
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; CHECK: ld2 {v0.16b, v1.16b}, [x0]
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; CHECK: st2 {v0.16b, v1.16b}, [x0]
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entry:
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%tobool22 = icmp eq i32 %count, 0
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br i1 %tobool22, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%count.addr.023 = phi i32 [ %dec, %while.body ], [ %count, %entry ]
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%dec = add i32 %count.addr.023, -1
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%vld2 = tail call { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8(i8* %io, i32 1)
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%vld2.fca.0.extract = extractvalue { <16 x i8>, <16 x i8> } %vld2, 0
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%vld2.fca.1.extract = extractvalue { <16 x i8>, <16 x i8> } %vld2, 1
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tail call void @llvm.arm.neon.vst2.v16i8(i8* %io, <16 x i8> %vld2.fca.0.extract, <16 x i8> %vld2.fca.1.extract, i32 1)
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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declare { <16 x i8>, <16 x i8> } @llvm.arm.neon.vld2.v16i8(i8*, i32)
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declare void @llvm.arm.neon.vst2.v16i8(i8*, <16 x i8>, <16 x i8>, i32)
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define void @test_ldst_4v(i8* noalias %io, i32 %count) {
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; CHECK-LABEL: test_ldst_4v
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; CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
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; CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
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entry:
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%tobool42 = icmp eq i32 %count, 0
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br i1 %tobool42, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%count.addr.043 = phi i32 [ %dec, %while.body ], [ %count, %entry ]
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%dec = add i32 %count.addr.043, -1
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%vld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8(i8* %io, i32 1)
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%vld4.fca.0.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %vld4, 0
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%vld4.fca.1.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %vld4, 1
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%vld4.fca.2.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %vld4, 2
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%vld4.fca.3.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %vld4, 3
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tail call void @llvm.arm.neon.vst4.v8i8(i8* %io, <8 x i8> %vld4.fca.0.extract, <8 x i8> %vld4.fca.1.extract, <8 x i8> %vld4.fca.2.extract, <8 x i8> %vld4.fca.3.extract, i32 1)
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld4.v8i8(i8*, i32)
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declare void @llvm.arm.neon.vst4.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32)
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define void @test_ldst_3v(i8* noalias %io, i32 %count) {
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; CHECK-LABEL: test_ldst_3v
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; CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0]
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; CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0]
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entry:
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%tobool32 = icmp eq i32 %count, 0
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br i1 %tobool32, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%count.addr.033 = phi i32 [ %dec, %while.body ], [ %count, %entry ]
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%dec = add i32 %count.addr.033, -1
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%vld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3.v8i8(i8* %io, i32 1)
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%vld3.fca.0.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vld3, 0
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%vld3.fca.1.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vld3, 1
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%vld3.fca.2.extract = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vld3, 2
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tail call void @llvm.arm.neon.vst3.v8i8(i8* %io, <8 x i8> %vld3.fca.0.extract, <8 x i8> %vld3.fca.1.extract, <8 x i8> %vld3.fca.2.extract, i32 1)
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.arm.neon.vld3.v8i8(i8*, i32)
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declare void @llvm.arm.neon.vst3.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32)
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define void @test_ldst_2v(i8* noalias %io, i32 %count) {
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; CHECK-LABEL: test_ldst_2v
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; CHECK: ld2 {v0.8b, v1.8b}, [x0]
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; CHECK: st2 {v0.8b, v1.8b}, [x0]
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entry:
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%tobool22 = icmp eq i32 %count, 0
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br i1 %tobool22, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%count.addr.023 = phi i32 [ %dec, %while.body ], [ %count, %entry ]
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%dec = add i32 %count.addr.023, -1
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%vld2 = tail call { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2.v8i8(i8* %io, i32 1)
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%vld2.fca.0.extract = extractvalue { <8 x i8>, <8 x i8> } %vld2, 0
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%vld2.fca.1.extract = extractvalue { <8 x i8>, <8 x i8> } %vld2, 1
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tail call void @llvm.arm.neon.vst2.v8i8(i8* %io, <8 x i8> %vld2.fca.0.extract, <8 x i8> %vld2.fca.1.extract, i32 1)
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%tobool = icmp eq i32 %dec, 0
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br i1 %tobool, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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declare { <8 x i8>, <8 x i8> } @llvm.arm.neon.vld2.v8i8(i8*, i32)
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declare void @llvm.arm.neon.vst2.v8i8(i8*, <8 x i8>, <8 x i8>, i32)
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