IR-gen should not generate an MMX types unless the code is explicitly using MMX
intrinsics. rdar://13213542 llvm-svn: 177911
This commit is contained in:
Chad Rosier
parent
f87f70a72d
commit
651c1839ee
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@ -480,11 +480,9 @@ ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
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ABIArgInfo::getExtend() : ABIArgInfo::getDirect());
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}
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/// UseX86_MMXType - Return true if this is an MMX type that should use the
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/// special x86_mmx type.
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bool UseX86_MMXType(llvm::Type *IRType) {
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// If the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>, use the
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// special x86_mmx type.
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/// IsX86_MMXType - Return true if this is an MMX type.
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bool IsX86_MMXType(llvm::Type *IRType) {
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// Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
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return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
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cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
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IRType->getScalarSizeInBits() != 64;
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@ -513,7 +511,6 @@ class X86_32ABIInfo : public ABIInfo {
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bool IsDarwinVectorABI;
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bool IsSmallStructInRegABI;
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bool IsMMXDisabled;
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bool IsWin32FloatStructABI;
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unsigned DefaultNumRegisterParameters;
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@ -546,18 +543,17 @@ public:
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virtual llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,
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CodeGenFunction &CGF) const;
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X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool m, bool w,
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X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool w,
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unsigned r)
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: ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p),
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IsMMXDisabled(m), IsWin32FloatStructABI(w),
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DefaultNumRegisterParameters(r) {}
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IsWin32FloatStructABI(w), DefaultNumRegisterParameters(r) {}
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};
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class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
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public:
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X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
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bool d, bool p, bool m, bool w, unsigned r)
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:TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, m, w, r)) {}
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bool d, bool p, bool w, unsigned r)
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:TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r)) {}
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void SetTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
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CodeGen::CodeGenModule &CGM) const;
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@ -910,15 +906,8 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty,
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Size));
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}
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llvm::Type *IRType = CGT.ConvertType(Ty);
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if (UseX86_MMXType(IRType)) {
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if (IsMMXDisabled)
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return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
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64));
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ABIArgInfo AAI = ABIArgInfo::getDirect(IRType);
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AAI.setCoerceToType(llvm::Type::getX86_MMXTy(getVMContext()));
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return AAI;
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}
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if (IsX86_MMXType(CGT.ConvertType(Ty)))
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return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
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return ABIArgInfo::getDirect();
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}
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@ -4881,11 +4870,9 @@ const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
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return *(TheTargetCodeGenInfo = new TCETargetCodeGenInfo(Types));
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case llvm::Triple::x86: {
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bool DisableMMX = strcmp(getContext().getTargetInfo().getABI(), "no-mmx") == 0;
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if (Triple.isOSDarwin())
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return *(TheTargetCodeGenInfo =
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new X86_32TargetCodeGenInfo(Types, true, true, DisableMMX, false,
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new X86_32TargetCodeGenInfo(Types, true, true, false,
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CodeGenOpts.NumRegisterParameters));
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switch (Triple.getOS()) {
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@ -4897,19 +4884,17 @@ const TargetCodeGenInfo &CodeGenModule::getTargetCodeGenInfo() {
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case llvm::Triple::OpenBSD:
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case llvm::Triple::Bitrig:
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return *(TheTargetCodeGenInfo =
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new X86_32TargetCodeGenInfo(Types, false, true, DisableMMX,
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false,
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new X86_32TargetCodeGenInfo(Types, false, true, false,
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CodeGenOpts.NumRegisterParameters));
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case llvm::Triple::Win32:
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return *(TheTargetCodeGenInfo =
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new X86_32TargetCodeGenInfo(Types, false, true, DisableMMX, true,
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new X86_32TargetCodeGenInfo(Types, false, true, true,
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CodeGenOpts.NumRegisterParameters));
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default:
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return *(TheTargetCodeGenInfo =
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new X86_32TargetCodeGenInfo(Types, false, false, DisableMMX,
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false,
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new X86_32TargetCodeGenInfo(Types, false, false, false,
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CodeGenOpts.NumRegisterParameters));
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}
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}
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@ -229,7 +229,7 @@ v4i32 f55(v4i32 arg) { return arg+arg; }
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// CHECK: define void @f56(
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// CHECK: i8 signext %a0, %struct.s56_0* byval align 4 %a1,
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// CHECK: x86_mmx %a2.coerce, %struct.s56_1* byval align 4,
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// CHECK: i64 %a2.coerce, %struct.s56_1* byval align 4,
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// CHECK: i64 %a4.coerce, %struct.s56_2* byval align 4,
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// CHECK: <4 x i32> %a6, %struct.s56_3* byval align 16 %a7,
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// CHECK: <2 x double> %a8, %struct.s56_4* byval align 16 %a9,
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@ -238,7 +238,7 @@ v4i32 f55(v4i32 arg) { return arg+arg; }
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// CHECK: call void (i32, ...)* @f56_0(i32 1,
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// CHECK: i32 %{{[^ ]*}}, %struct.s56_0* byval align 4 %{{[^ ]*}},
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// CHECK: x86_mmx %{{[^ ]*}}, %struct.s56_1* byval align 4 %{{[^ ]*}},
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// CHECK: i64 %{{[^ ]*}}, %struct.s56_1* byval align 4 %{{[^ ]*}},
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// CHECK: i64 %{{[^ ]*}}, %struct.s56_2* byval align 4 %{{[^ ]*}},
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// CHECK: <4 x i32> %{{[^ ]*}}, %struct.s56_3* byval align 16 %{{[^ ]*}},
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// CHECK: <2 x double> %{{[^ ]*}}, %struct.s56_4* byval align 16 %{{[^ ]*}},
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@ -3,7 +3,7 @@
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// CHECK: define void @f56(
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// CHECK: i8 signext %a0, %struct.s56_0* byval align 4 %a1,
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// CHECK: x86_mmx %a2.coerce, %struct.s56_1* byval align 4,
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// CHECK: i64 %a2.coerce, %struct.s56_1* byval align 4,
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// CHECK: <1 x double> %a4, %struct.s56_2* byval align 4,
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// CHECK: <4 x i32> %a6, %struct.s56_3* byval align 4,
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// CHECK: <2 x double> %a8, %struct.s56_4* byval align 4,
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@ -12,7 +12,7 @@
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// CHECK: call void (i32, ...)* @f56_0(i32 1,
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// CHECK: i32 %{{.*}}, %struct.s56_0* byval align 4 %{{[^ ]*}},
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// CHECK: x86_mmx %{{[^ ]*}}, %struct.s56_1* byval align 4 %{{[^ ]*}},
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// CHECK: i64 %{{[^ ]*}}, %struct.s56_1* byval align 4 %{{[^ ]*}},
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// CHECK: <1 x double> %{{[^ ]*}}, %struct.s56_2* byval align 4 %{{[^ ]*}},
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// CHECK: <4 x i32> %{{[^ ]*}}, %struct.s56_3* byval align 4 %{{[^ ]*}},
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// CHECK: <2 x double> %{{[^ ]*}}, %struct.s56_4* byval align 4 %{{[^ ]*}},
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