[scudo] Enabling MIPS support for Scudo
Adding MIPS 32-bit and 64-bit support for Scudo. Reviewed by cryptoad, sdardis. Differential: D31803 llvm-svn: 305682
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@ -179,7 +179,7 @@ set(ALL_UBSAN_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64}
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set(ALL_SAFESTACK_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM64} ${MIPS32} ${MIPS64})
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set(ALL_CFI_SUPPORTED_ARCH ${X86} ${X86_64} ${MIPS64})
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set(ALL_ESAN_SUPPORTED_ARCH ${X86_64} ${MIPS64})
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set(ALL_SCUDO_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64})
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set(ALL_SCUDO_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64})
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set(ALL_XRAY_SUPPORTED_ARCH ${X86_64} ${ARM32} ${ARM64} ${MIPS32} ${MIPS64} powerpc64le)
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if(APPLE)
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@ -71,16 +71,26 @@ INLINE typename T::Type atomic_exchange(volatile T *a,
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return v;
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}
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template<typename T>
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INLINE bool atomic_compare_exchange_strong(volatile T *a,
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typename T::Type *cmp,
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template <typename T>
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INLINE bool atomic_compare_exchange_strong(volatile T *a, typename T::Type *cmp,
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typename T::Type xchg,
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memory_order mo) {
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typedef typename T::Type Type;
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Type cmpv = *cmp;
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Type prev = __sync_val_compare_and_swap(&a->val_dont_use, cmpv, xchg);
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if (prev == cmpv)
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return true;
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Type prev;
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#if defined(_MIPS_SIM) && _MIPS_SIM == _ABIO32
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if (sizeof(*a) == 8) {
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Type volatile *val_ptr = const_cast<Type volatile *>(&a->val_dont_use);
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prev = __mips_sync_val_compare_and_swap<u64>(
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reinterpret_cast<u64 volatile *>(val_ptr), reinterpret_cast<u64> cmpv,
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reinterpret_cast<u64> xchg);
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} else {
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prev = __sync_val_compare_and_swap(&a->val_dont_use, cmpv, xchg);
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}
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#else
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prev = __sync_val_compare_and_swap(&a->val_dont_use, cmpv, xchg);
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#endif
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if (prev == cmpv) return true;
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*cmp = prev;
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return false;
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}
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@ -17,6 +17,56 @@
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namespace __sanitizer {
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// MIPS32 does not support atomic > 4 bytes. To address this lack of
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// functionality, the sanitizer library provides helper methods which use an
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// internal spin lock mechanism to emulate atomic oprations when the size is
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// 8 bytes.
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#if defined(_MIPS_SIM) && _MIPS_SIM == _ABIO32
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static void __spin_lock(volatile int *lock) {
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while (__sync_lock_test_and_set(lock, 1))
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while (*lock) {
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}
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}
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static void __spin_unlock(volatile int *lock) { __sync_lock_release(lock); }
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// Make sure the lock is on its own cache line to prevent false sharing.
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// Put it inside a struct that is aligned and padded to the typical MIPS
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// cacheline which is 32 bytes.
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static struct {
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int lock;
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char pad[32 - sizeof(int)];
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} __attribute__((aligned(32))) lock = {0};
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template <class T>
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T __mips_sync_fetch_and_add(volatile T *ptr, T val) {
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T ret;
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__spin_lock(&lock.lock);
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ret = *ptr;
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*ptr = ret + val;
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__spin_unlock(&lock.lock);
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return ret;
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}
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template <class T>
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T __mips_sync_val_compare_and_swap(volatile T *ptr, T oldval, T newval) {
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T ret;
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__spin_lock(&lock.lock);
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ret = *ptr;
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if (ret == oldval) *ptr = newval;
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__spin_unlock(&lock.lock);
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return ret;
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}
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#endif
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INLINE void proc_yield(int cnt) {
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__asm__ __volatile__("" ::: "memory");
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}
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@ -53,8 +103,15 @@ INLINE typename T::Type atomic_load(
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// 64-bit load on 32-bit platform.
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// Gross, but simple and reliable.
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// Assume that it is not in read-only memory.
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#if defined(_MIPS_SIM) && _MIPS_SIM == _ABIO32
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typename T::Type volatile *val_ptr =
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const_cast<typename T::Type volatile *>(&a->val_dont_use);
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v = __mips_sync_fetch_and_add<u64>(
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reinterpret_cast<u64 volatile *>(val_ptr), 0);
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#else
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v = __sync_fetch_and_add(
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const_cast<typename T::Type volatile *>(&a->val_dont_use), 0);
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#endif
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}
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return v;
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}
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@ -84,7 +141,15 @@ INLINE void atomic_store(volatile T *a, typename T::Type v, memory_order mo) {
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typename T::Type cmp = a->val_dont_use;
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typename T::Type cur;
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for (;;) {
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#if defined(_MIPS_SIM) && _MIPS_SIM == _ABIO32
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typename T::Type volatile *val_ptr =
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const_cast<typename T::Type volatile *>(&a->val_dont_use);
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cur = __mips_sync_val_compare_and_swap<u64>(
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reinterpret_cast<u64 volatile *>(val_ptr), reinterpret_cast<u64> cmp,
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reinterpret_cast<u64> v);
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#else
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cur = __sync_val_compare_and_swap(&a->val_dont_use, cmp, v);
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#endif
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if (cmp == v)
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break;
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cmp = cur;
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@ -7,7 +7,7 @@
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// RUN: %run %t 10000 > %T/random_shuffle_tmp_dir/out2
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// RUN: not diff %T/random_shuffle_tmp_dir/out?
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// RUN: rm -rf %T/random_shuffle_tmp_dir
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// UNSUPPORTED: i386-linux,i686-linux,arm-linux,armhf-linux,aarch64-linux
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// UNSUPPORTED: i386-linux,i686-linux,arm-linux,armhf-linux,aarch64-linux,mips-linux,mipsel-linux,mips64-linux,mips64el-linux
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// Tests that the allocator shuffles the chunks before returning to the user.
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