Fix two bugs in 104348:
Case where MMX is disabled wasn't handled right. MMX->MMX bitconverts are Legal. llvm-svn: 104336
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3fe900e410
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@ -217,10 +217,13 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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if (!X86ScalarSSEf64) {
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if (!X86ScalarSSEf64) {
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setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
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setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
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setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
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setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
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if (Subtarget->is64Bit() && Subtarget->hasMMX() && !DisableMMX) {
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if (Subtarget->is64Bit()) {
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// Without SSE, i64->f64 goes through memory; i64->MMX is legal.
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setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
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setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
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setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
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// Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
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if (Subtarget->hasMMX() && !DisableMMX)
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setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
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else
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setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
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}
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}
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}
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}
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@ -7486,6 +7489,9 @@ SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
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return Op;
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return Op;
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if (DstVT==MVT::i64 && SrcVT.isVector())
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if (DstVT==MVT::i64 && SrcVT.isVector())
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return Op;
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return Op;
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// MMX <=> MMX conversions are Legal.
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if (SrcVT.isVector() && DstVT.isVector())
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return Op;
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// All other conversions need to be expanded.
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// All other conversions need to be expanded.
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return SDValue();
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return SDValue();
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}
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}
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