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CodeGen: TII: Take MachineInstr& in predicate API, NFC 

Change TargetInstrInfo API to take `MachineInstr&` instead of
`MachineInstr*` in the functions related to predicated instructions
(I'll try to come back later and get some of the rest).  All of these
functions require non-null parameters already, so references are more
clear.  As a bonus, this happens to factor away a host of implicit
iterator => pointer conversions.

No functionality change intended.

llvm-svn: 261605
This commit is contained in:
Duncan P. N. Exon Smith 2016-02-23 02:46:52 +00:00
parent b3613fce19
commit 6307eb5518
47 changed files with 388 additions and 408 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
llvm/include/llvm/Target/TargetInstrInfo.h
View File

@ -1010,19 +1010,18 @@ public:
/// Returns true if the instruction is already predicated.
virtual bool isPredicated(const MachineInstr *MI) const {
virtual bool isPredicated(const MachineInstr &MI) const {
return false;
}
/// Returns true if the instruction is a
/// terminator instruction that has not been predicated.
virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
/// Convert the instruction into a predicated instruction.
/// It returns true if the operation was successful.
virtual
bool PredicateInstruction(MachineInstr *MI,
ArrayRef<MachineOperand> Pred) const;
virtual bool PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const;
/// Returns true if the first specified predicate
/// subsumes the second, e.g. GE subsumes GT.
@ -1035,7 +1034,7 @@ public:
/// If the specified instruction defines any predicate
/// or condition code register(s) used for predication, returns true as well
/// as the definition predicate(s) by reference.
virtual bool DefinesPredicate(MachineInstr *MI,
virtual bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const {
return false;
}
@ -1043,8 +1042,8 @@ public:
/// Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a
/// PredicateOperand.
virtual bool isPredicable(MachineInstr *MI) const {
return MI->getDesc().isPredicable();
virtual bool isPredicable(MachineInstr &MI) const {
return MI.getDesc().isPredicable();
}
/// Return true if it's safe to move a machine
@ -1178,7 +1177,7 @@ public:
const MachineInstr *MI,
unsigned *PredCost = nullptr) const;
virtual unsigned getPredicationCost(const MachineInstr *MI) const;
virtual unsigned getPredicationCost(const MachineInstr &MI) const;
virtual int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const;

7
llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
View File

@ -368,7 +368,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
// reference either system calls or the register directly. Skip it until we
// can tell user specified registers from compiler-specified.
if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
TII->isPredicated(MI) || MI->isInlineAsm()) {
TII->isPredicated(*MI) || MI->isInlineAsm()) {
DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
State->UnionGroups(Reg, 0);
}
@ -444,9 +444,8 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
// instruction which may not be executed. The second R6 def may or may not
// re-define R6 so it's not safe to change it since the last R6 use cannot be
// changed.
bool Special = MI->isCall() ||
MI->hasExtraSrcRegAllocReq() ||
TII->isPredicated(MI) || MI->isInlineAsm();
bool Special = MI->isCall() || MI->hasExtraSrcRegAllocReq() ||
TII->isPredicated(*MI) || MI->isInlineAsm();
// Scan the register uses for this instruction and update
// live-ranges, groups and RegRefs.

8
llvm/lib/CodeGen/BranchFolding.cpp
View File

@ -167,7 +167,7 @@ bool BranchFolder::OptimizeImpDefsBlock(MachineBasicBlock *MBB) {
MachineBasicBlock::iterator FirstTerm = I;
while (I != MBB->end()) {
if (!TII->isUnpredicatedTerminator(I))
if (!TII->isUnpredicatedTerminator(*I))
return false;
// See if it uses any of the implicitly defined registers.
for (const MachineOperand &MO : I->operands()) {
@ -1623,7 +1623,7 @@ MachineBasicBlock::iterator findHoistingInsertPosAndDeps(MachineBasicBlock *MBB,
SmallSet<unsigned,4> &Uses,
SmallSet<unsigned,4> &Defs) {
MachineBasicBlock::iterator Loc = MBB->getFirstTerminator();
if (!TII->isUnpredicatedTerminator(Loc))
if (!TII->isUnpredicatedTerminator(*Loc))
return MBB->end();
for (const MachineOperand &MO : Loc->operands()) {
@ -1685,7 +1685,7 @@ MachineBasicBlock::iterator findHoistingInsertPosAndDeps(MachineBasicBlock *MBB,
// Also avoid moving code above predicated instruction since it's hard to
// reason about register liveness with predicated instruction.
bool DontMoveAcrossStore = true;
if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(PI))
if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(*PI))
return MBB->end();
@ -1765,7 +1765,7 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) {
if (!TIB->isIdenticalTo(FIB, MachineInstr::CheckKillDead))
break;
if (TII->isPredicated(TIB))
if (TII->isPredicated(*TIB))
// Hard to reason about register liveness with predicated instruction.
break;

9
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -163,9 +163,8 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
// instruction which may not be executed. The second R6 def may or may not
// re-define R6 so it's not safe to change it since the last R6 use cannot be
// changed.
bool Special = MI->isCall() ||
MI->hasExtraSrcRegAllocReq() ||
TII->isPredicated(MI);
bool Special =
MI->isCall() || MI->hasExtraSrcRegAllocReq() || TII->isPredicated(*MI);
// Scan the register operands for this instruction and update
// Classes and RegRefs.
@ -241,7 +240,7 @@ void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
// instruction are now dead.
assert(!MI->isKill() && "Attempting to scan a kill instruction");
if (!TII->isPredicated(MI)) {
if (!TII->isPredicated(*MI)) {
// Predicated defs are modeled as read + write, i.e. similar to two
// address updates.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@ -585,7 +584,7 @@ BreakAntiDependencies(const std::vector<SUnit>& SUnits,
// If MI's defs have a special allocation requirement, don't allow
// any def registers to be changed. Also assume all registers
// defined in a call must not be changed (ABI).
if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(MI))
if (MI->isCall() || MI->hasExtraDefRegAllocReq() || TII->isPredicated(*MI))
// If this instruction's defs have special allocation requirement, don't
// break this anti-dependency.
AntiDepReg = 0;

54
llvm/lib/CodeGen/IfConversion.cpp
View File

@ -668,16 +668,15 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
BBI.ExtraCost = 0;
BBI.ExtraCost2 = 0;
BBI.ClobbersPred = false;
for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
I != E; ++I) {
if (I->isDebugValue())
for (auto &MI : *BBI.BB) {
if (MI.isDebugValue())
continue;
if (I->isNotDuplicable())
if (MI.isNotDuplicable())
BBI.CannotBeCopied = true;
bool isPredicated = TII->isPredicated(I);
bool isCondBr = BBI.IsBrAnalyzable && I->isConditionalBranch();
bool isPredicated = TII->isPredicated(MI);
bool isCondBr = BBI.IsBrAnalyzable && MI.isConditionalBranch();
// A conditional branch is not predicable, but it may be eliminated.
if (isCondBr)
@ -685,8 +684,8 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
if (!isPredicated) {
BBI.NonPredSize++;
unsigned ExtraPredCost = TII->getPredicationCost(&*I);
unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
unsigned ExtraPredCost = TII->getPredicationCost(MI);
unsigned NumCycles = SchedModel.computeInstrLatency(&MI, false);
if (NumCycles > 1)
BBI.ExtraCost += NumCycles-1;
BBI.ExtraCost2 += ExtraPredCost;
@ -710,10 +709,10 @@ void IfConverter::ScanInstructions(BBInfo &BBI) {
// FIXME: Make use of PredDefs? e.g. ADDC, SUBC sets predicates but are
// still potentially predicable.
std::vector<MachineOperand> PredDefs;
if (TII->DefinesPredicate(I, PredDefs))
if (TII->DefinesPredicate(MI, PredDefs))
BBI.ClobbersPred = true;
if (!TII->isPredicable(I)) {
if (!TII->isPredicable(MI)) {
BBI.IsUnpredicable = true;
return;
}
@ -1011,9 +1010,9 @@ void IfConverter::RemoveExtraEdges(BBInfo &BBI) {
/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
/// values defined in MI which are not live/used by MI.
static void UpdatePredRedefs(MachineInstr *MI, LivePhysRegs &Redefs) {
static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Clobbers;
Redefs.stepForward(*MI, Clobbers);
Redefs.stepForward(MI, Clobbers);
// Now add the implicit uses for each of the clobbered values.
for (auto Reg : Clobbers) {
@ -1491,8 +1490,8 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
if (!BBI2->BB->empty() && (DI2 == BBI2->BB->end())) {
MachineBasicBlock::iterator BBI1T = BBI1->BB->getFirstTerminator();
MachineBasicBlock::iterator BBI2T = BBI2->BB->getFirstTerminator();
if ((BBI1T != BBI1->BB->end()) && TII->isPredicated(BBI1T) &&
((BBI2T != BBI2->BB->end()) && !TII->isPredicated(BBI2T)))
if (BBI1T != BBI1->BB->end() && TII->isPredicated(*BBI1T) &&
BBI2T != BBI2->BB->end() && !TII->isPredicated(*BBI2T))
--DI2;
}
@ -1515,7 +1514,7 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
// (e.g. a predicated return). If that is the case, we cannot merge
// it with the tail block.
MachineBasicBlock::const_iterator TI = BBI.BB->getFirstTerminator();
if (TI != BBI.BB->end() && TII->isPredicated(TI))
if (TI != BBI.BB->end() && TII->isPredicated(*TI))
CanMergeTail = false;
// There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
// check if there are any other predecessors besides those.
@ -1581,7 +1580,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
bool AnyUnpred = false;
bool MaySpec = LaterRedefs != nullptr;
for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
if (I->isDebugValue() || TII->isPredicated(I))
if (I->isDebugValue() || TII->isPredicated(*I))
continue;
// It may be possible not to predicate an instruction if it's the 'true'
// side of a diamond and the 'false' side may re-define the instruction's
@ -1593,7 +1592,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
// If any instruction is predicated, then every instruction after it must
// be predicated.
MaySpec = false;
if (!TII->PredicateInstruction(I, Cond)) {
if (!TII->PredicateInstruction(*I, Cond)) {
#ifndef NDEBUG
dbgs() << "Unable to predicate " << *I << "!\n";
#endif
@ -1602,7 +1601,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
// If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
UpdatePredRedefs(I, Redefs);
UpdatePredRedefs(*I, Redefs);
}
BBI.Predicate.append(Cond.begin(), Cond.end());
@ -1622,25 +1621,24 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
bool IgnoreBr) {
MachineFunction &MF = *ToBBI.BB->getParent();
for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
E = FromBBI.BB->end(); I != E; ++I) {
for (auto &I : *FromBBI.BB) {
// Do not copy the end of the block branches.
if (IgnoreBr && I->isBranch())
if (IgnoreBr && I.isBranch())
break;
MachineInstr *MI = MF.CloneMachineInstr(I);
MachineInstr *MI = MF.CloneMachineInstr(&I);
ToBBI.BB->insert(ToBBI.BB->end(), MI);
ToBBI.NonPredSize++;
unsigned ExtraPredCost = TII->getPredicationCost(&*I);
unsigned NumCycles = SchedModel.computeInstrLatency(&*I, false);
unsigned ExtraPredCost = TII->getPredicationCost(I);
unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);
if (NumCycles > 1)
ToBBI.ExtraCost += NumCycles-1;
ToBBI.ExtraCost2 += ExtraPredCost;
if (!TII->isPredicated(I) && !MI->isDebugValue()) {
if (!TII->PredicateInstruction(MI, Cond)) {
if (!TII->PredicateInstruction(*MI, Cond)) {
#ifndef NDEBUG
dbgs() << "Unable to predicate " << *I << "!\n";
dbgs() << "Unable to predicate " << I << "!\n";
#endif
llvm_unreachable(nullptr);
}
@ -1648,7 +1646,7 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
// If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
UpdatePredRedefs(MI, Redefs);
UpdatePredRedefs(*MI, Redefs);
// Some kill flags may not be correct anymore.
if (!DontKill.empty())
@ -1695,7 +1693,7 @@ void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) {
ToBBI.BB->splice(ToTI, FromBBI.BB, FromBBI.BB->begin(), FromTI);
// If FromBB has non-predicated terminator we should copy it at the end.
if ((FromTI != FromBBI.BB->end()) && !TII->isPredicated(FromTI))
if (FromTI != FromBBI.BB->end() && !TII->isPredicated(*FromTI))
ToTI = ToBBI.BB->end();
ToBBI.BB->splice(ToTI, FromBBI.BB, FromTI, FromBBI.BB->end());

2
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -691,7 +691,7 @@ bool MachineBasicBlock::canFallThrough() {
// is possible. The isPredicated check is needed because this code can be
// called during IfConversion, where an instruction which is normally a
// Barrier is predicated and thus no longer an actual control barrier.
return empty() || !back().isBarrier() || TII->isPredicated(&back());
return empty() || !back().isBarrier() || TII->isPredicated(back());
}
// If there is no branch, control always falls through.

4
llvm/lib/CodeGen/MachineVerifier.cpp
View File

@ -630,7 +630,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
"differs from its CFG successor!", MBB);
}
if (!MBB->empty() && MBB->back().isBarrier() &&
!TII->isPredicated(&MBB->back())) {
!TII->isPredicated(MBB->back())) {
report("MBB exits via unconditional fall-through but ends with a "
"barrier instruction!", MBB);
}
@ -772,7 +772,7 @@ void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
// Ensure non-terminators don't follow terminators.
// Ignore predicated terminators formed by if conversion.
// FIXME: If conversion shouldn't need to violate this rule.
if (MI->isTerminator() && !TII->isPredicated(MI)) {
if (MI->isTerminator() && !TII->isPredicated(*MI)) {
if (!FirstTerminator)
FirstTerminator = MI;
} else if (FirstTerminator) {

23
llvm/lib/CodeGen/TargetInstrInfo.cpp
View File

@ -256,32 +256,31 @@ bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
return true;
}
bool
TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
if (!MI->isTerminator()) return false;
bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
if (!MI.isTerminator()) return false;
// Conditional branch is a special case.
if (MI->isBranch() && !MI->isBarrier())
if (MI.isBranch() && !MI.isBarrier())
return true;
if (!MI->isPredicable())
if (!MI.isPredicable())
return true;
return !isPredicated(MI);
}
bool TargetInstrInfo::PredicateInstruction(
MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
bool MadeChange = false;
assert(!MI->isBundle() &&
assert(!MI.isBundle() &&
"TargetInstrInfo::PredicateInstruction() can't handle bundles");
const MCInstrDesc &MCID = MI->getDesc();
if (!MI->isPredicable())
const MCInstrDesc &MCID = MI.getDesc();
if (!MI.isPredicable())
return false;
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
for (unsigned j = 0, i = 0, e = MI.getNumOperands(); i != e; ++i) {
if (MCID.OpInfo[i].isPredicate()) {
MachineOperand &MO = MI->getOperand(i);
MachineOperand &MO = MI.getOperand(i);
if (MO.isReg()) {
MO.setReg(Pred[j].getReg());
MadeChange = true;
@ -1035,7 +1034,7 @@ unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
return 1;
}
unsigned TargetInstrInfo::getPredicationCost(const MachineInstr *) const {
unsigned TargetInstrInfo::getPredicationCost(const MachineInstr &) const {
return 0;
}

2
llvm/lib/CodeGen/TargetSchedule.cpp
View File

@ -282,7 +282,7 @@ computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
const MachineFunction &MF = *DefMI->getParent()->getParent();
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(DepMI))
if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
return computeInstrLatency(DefMI);
// If we have a per operand scheduling model, check if this def is writing

8
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -99,7 +99,7 @@ bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
if (I == MBB.end())
return false;
if (!isUnpredicatedTerminator(I))
if (!isUnpredicatedTerminator(*I))
return false;
// Get the last instruction in the block.
@ -107,7 +107,7 @@ bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
if (isUncondBranchOpcode(LastOpc)) {
TBB = LastInst->getOperand(0).getMBB();
return false;
@ -131,7 +131,7 @@ bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
LastInst->eraseFromParent();
LastInst = SecondLastInst;
LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
// Return now the only terminator is an unconditional branch.
TBB = LastInst->getOperand(0).getMBB();
return false;
@ -143,7 +143,7 @@ bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
}
// If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
return true;
// If the block ends with a B and a Bcc, handle it.

57
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
View File

@ -876,13 +876,12 @@ R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
return 2;
}
bool
R600InstrInfo::isPredicated(const MachineInstr *MI) const {
int idx = MI->findFirstPredOperandIdx();
bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
int idx = MI.findFirstPredOperandIdx();
if (idx < 0)
return false;
unsigned Reg = MI->getOperand(idx).getReg();
unsigned Reg = MI.getOperand(idx).getReg();
switch (Reg) {
default: return false;
case AMDGPU::PRED_SEL_ONE:
@ -892,25 +891,24 @@ R600InstrInfo::isPredicated(const MachineInstr *MI) const {
}
}
bool
R600InstrInfo::isPredicable(MachineInstr *MI) const {
bool R600InstrInfo::isPredicable(MachineInstr &MI) const {
// XXX: KILL* instructions can be predicated, but they must be the last
// instruction in a clause, so this means any instructions after them cannot
// be predicated. Until we have proper support for instruction clauses in the
// backend, we will mark KILL* instructions as unpredicable.
if (MI->getOpcode() == AMDGPU::KILLGT) {
if (MI.getOpcode() == AMDGPU::KILLGT) {
return false;
} else if (MI->getOpcode() == AMDGPU::CF_ALU) {
} else if (MI.getOpcode() == AMDGPU::CF_ALU) {
// If the clause start in the middle of MBB then the MBB has more
// than a single clause, unable to predicate several clauses.
if (MI->getParent()->begin() != MachineBasicBlock::iterator(MI))
if (MI.getParent()->begin() != MachineBasicBlock::iterator(MI))
return false;
// TODO: We don't support KC merging atm
if (MI->getOperand(3).getImm() != 0 || MI->getOperand(4).getImm() != 0)
if (MI.getOperand(3).getImm() != 0 || MI.getOperand(4).getImm() != 0)
return false;
return true;
} else if (isVector(*MI)) {
} else if (isVector(MI)) {
return false;
} else {
return AMDGPUInstrInfo::isPredicable(MI);
@ -986,10 +984,9 @@ R600InstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) con
return false;
}
bool
R600InstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
return isPredicateSetter(MI->getOpcode());
bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const {
return isPredicateSetter(MI.getOpcode());
}
@ -999,35 +996,33 @@ R600InstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
return false;
}
bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const {
int PIdx = MI.findFirstPredOperandIdx();
bool
R600InstrInfo::PredicateInstruction(MachineInstr *MI,
ArrayRef<MachineOperand> Pred) const {
int PIdx = MI->findFirstPredOperandIdx();
if (MI->getOpcode() == AMDGPU::CF_ALU) {
MI->getOperand(8).setImm(0);
if (MI.getOpcode() == AMDGPU::CF_ALU) {
MI.getOperand(8).setImm(0);
return true;
}
if (MI->getOpcode() == AMDGPU::DOT_4) {
MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X))
if (MI.getOpcode() == AMDGPU::DOT_4) {
MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_X))
.setReg(Pred[2].getReg());
MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y))
MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Y))
.setReg(Pred[2].getReg());
MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z))
MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_Z))
.setReg(Pred[2].getReg());
MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W))
MI.getOperand(getOperandIdx(MI, AMDGPU::OpName::pred_sel_W))
.setReg(Pred[2].getReg());
MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
return true;
}
if (PIdx != -1) {
MachineOperand &PMO = MI->getOperand(PIdx);
MachineOperand &PMO = MI.getOperand(PIdx);
PMO.setReg(Pred[2].getReg());
MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
return true;
}
@ -1035,7 +1030,7 @@ R600InstrInfo::PredicateInstruction(MachineInstr *MI,
return false;
}
unsigned int R600InstrInfo::getPredicationCost(const MachineInstr *) const {
unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
return 2;
}

12
llvm/lib/Target/AMDGPU/R600InstrInfo.h
View File

@ -168,9 +168,9 @@ namespace llvm {
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
bool isPredicated(const MachineInstr *MI) const override;
bool isPredicated(const MachineInstr &MI) const override;
bool isPredicable(MachineInstr *MI) const override;
bool isPredicable(MachineInstr &MI) const override;
bool
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
@ -187,8 +187,8 @@ namespace llvm {
unsigned NumFCycles, unsigned ExtraFCycles,
BranchProbability Probability) const override;
bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override;
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
ArrayRef<MachineOperand> Pred2) const override;
@ -196,10 +196,10 @@ namespace llvm {
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
MachineBasicBlock &FMBB) const override;
bool PredicateInstruction(MachineInstr *MI,
bool PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const override;
unsigned int getPredicationCost(const MachineInstr *) const override;
unsigned int getPredicationCost(const MachineInstr &) const override;
unsigned int getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,

2
llvm/lib/Target/AMDGPU/R600Packetizer.cpp
View File

@ -85,7 +85,7 @@ private:
if (LastDstChan >= BISlot)
isTrans = true;
LastDstChan = BISlot;
if (TII->isPredicated(&*BI))
if (TII->isPredicated(*BI))
continue;
int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)

96
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -289,7 +289,7 @@ ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// Walk backwards from the end of the basic block until the branch is
// analyzed or we give up.
while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
// Flag to be raised on unanalyzeable instructions. This is useful in cases
// where we want to clean up on the end of the basic block before we bail
@ -322,7 +322,7 @@ ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
Cond.push_back(I->getOperand(2));
} else if (I->isReturn()) {
// Returns can't be analyzed, but we should run cleanup.
CantAnalyze = !isPredicated(I);
CantAnalyze = !isPredicated(*I);
} else {
// We encountered other unrecognized terminator. Bail out immediately.
return true;
@ -330,7 +330,7 @@ ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
// Cleanup code - to be run for unpredicated unconditional branches and
// returns.
if (!isPredicated(I) &&
if (!isPredicated(*I) &&
(isUncondBranchOpcode(I->getOpcode()) ||
isIndirectBranchOpcode(I->getOpcode()) ||
isJumpTableBranchOpcode(I->getOpcode()) ||
@ -438,10 +438,10 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
return false;
}
bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
if (MI->isBundle()) {
MachineBasicBlock::const_instr_iterator I = MI->getIterator();
MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
if (MI.isBundle()) {
MachineBasicBlock::const_instr_iterator I = MI.getIterator();
MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
while (++I != E && I->isInsideBundle()) {
int PIdx = I->findFirstPredOperandIdx();
if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
@ -450,26 +450,26 @@ bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
return false;
}
int PIdx = MI->findFirstPredOperandIdx();
return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
int PIdx = MI.findFirstPredOperandIdx();
return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
}
bool ARMBaseInstrInfo::
PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
unsigned Opc = MI->getOpcode();
bool ARMBaseInstrInfo::PredicateInstruction(
MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
unsigned Opc = MI.getOpcode();
if (isUncondBranchOpcode(Opc)) {
MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(Pred[0].getImm())
.addReg(Pred[1].getReg());
return true;
}
int PIdx = MI->findFirstPredOperandIdx();
int PIdx = MI.findFirstPredOperandIdx();
if (PIdx != -1) {
MachineOperand &PMO = MI->getOperand(PIdx);
MachineOperand &PMO = MI.getOperand(PIdx);
PMO.setImm(Pred[0].getImm());
MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
return true;
}
return false;
@ -501,11 +501,11 @@ bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
}
}
bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
bool ARMBaseInstrInfo::DefinesPredicate(
MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
(MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
Pred.push_back(MO);
@ -555,21 +555,21 @@ static bool isEligibleForITBlock(const MachineInstr *MI) {
/// isPredicable - Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a
/// PredicateOperand.
bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
if (!MI->isPredicable())
bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const {
if (!MI.isPredicable())
return false;
if (!isEligibleForITBlock(MI))
if (!isEligibleForITBlock(&MI))
return false;
ARMFunctionInfo *AFI =
MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
MI.getParent()->getParent()->getInfo<ARMFunctionInfo>();
if (AFI->isThumb2Function()) {
if (getSubtarget().restrictIT())
return isV8EligibleForIT(MI);
return isV8EligibleForIT(&MI);
} else { // non-Thumb
if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
return false;
}
@ -1718,7 +1718,7 @@ isProfitableToIfCvt(MachineBasicBlock &MBB,
CmpMI->getOpcode() == ARM::t2CMPri) {
unsigned Reg = CmpMI->getOperand(0).getReg();
unsigned PredReg = 0;
ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg);
ARMCC::CondCodes P = getInstrPredicate(*CmpMI, PredReg);
if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
isARMLowRegister(Reg))
return false;
@ -1773,16 +1773,16 @@ ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
/// getInstrPredicate - If instruction is predicated, returns its predicate
/// condition, otherwise returns AL. It also returns the condition code
/// register by reference.
ARMCC::CondCodes
llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
int PIdx = MI->findFirstPredOperandIdx();
ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI,
unsigned &PredReg) {
int PIdx = MI.findFirstPredOperandIdx();
if (PIdx == -1) {
PredReg = 0;
return ARMCC::AL;
}
PredReg = MI->getOperand(PIdx+1).getReg();
return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
PredReg = MI.getOperand(PIdx+1).getReg();
return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
}
@ -1806,7 +1806,7 @@ MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr *MI,
case ARM::t2MOVCCr: {
// MOVCC can be commuted by inverting the condition.
unsigned PredReg = 0;
ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
ARMCC::CondCodes CC = getInstrPredicate(*MI, PredReg);
// MOVCC AL can't be inverted. Shouldn't happen.
if (CC == ARMCC::AL || PredReg != ARM::CPSR)
return nullptr;
@ -2395,7 +2395,7 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
// Masked compares sometimes use the same register as the corresponding 'and'.
if (CmpMask != ~0) {
if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
MI = nullptr;
for (MachineRegisterInfo::use_instr_iterator
UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
@ -2403,7 +2403,7 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
if (UI->getParent() != CmpInstr->getParent()) continue;
MachineInstr *PotentialAND = &*UI;
if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
isPredicated(PotentialAND))
isPredicated(*PotentialAND))
continue;
MI = PotentialAND;
break;
@ -2471,7 +2471,7 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
if (!MI) MI = Sub;
// We can't use a predicated instruction - it doesn't always write the flags.
if (isPredicated(MI))
if (isPredicated(*MI))
return false;
switch (MI->getOpcode()) {
@ -2618,7 +2618,7 @@ optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
// Toggle the optional operand to CPSR.
MI->getOperand(5).setReg(ARM::CPSR);
MI->getOperand(5).setIsDef(true);
assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
CmpInstr->eraseFromParent();
// Modify the condition code of operands in OperandsToUpdate.
@ -3946,15 +3946,15 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
return Latency;
}
unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
if (MI->isCopyLike() || MI->isInsertSubreg() ||
MI->isRegSequence() || MI->isImplicitDef())
unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
MI.isImplicitDef())
return 0;
if (MI->isBundle())
if (MI.isBundle())
return 0;
const MCInstrDesc &MCID = MI->getDesc();
const MCInstrDesc &MCID = MI.getDesc();
if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
// When predicated, CPSR is an additional source operand for CPSR updating
@ -4152,12 +4152,12 @@ ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
if (Subtarget.hasNEON()) {
// VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
// if they are not predicated.
if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
if (MI->getOpcode() == ARM::VMOVD && !isPredicated(*MI))
return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
// CortexA9 is particularly picky about mixing the two and wants these
// converted.
if (Subtarget.isCortexA9() && !isPredicated(MI) &&
if (Subtarget.isCortexA9() && !isPredicated(*MI) &&
(MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
MI->getOpcode() == ARM::VMOVS))
return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
@ -4252,7 +4252,7 @@ ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
break;
// Zap the predicate operands.
assert(!isPredicated(MI) && "Cannot predicate a VORRd");
assert(!isPredicated(*MI) && "Cannot predicate a VORRd");
// Make sure we've got NEON instructions.
assert(Subtarget.hasNEON() && "VORRd requires NEON");
@ -4273,7 +4273,7 @@ ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
case ARM::VMOVRS:
if (Domain != ExeNEON)
break;
assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
assert(!isPredicated(*MI) && "Cannot predicate a VGETLN");
// Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
DstReg = MI->getOperand(0).getReg();
@ -4299,7 +4299,7 @@ ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
case ARM::VMOVSR: {
if (Domain != ExeNEON)
break;
assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
assert(!isPredicated(*MI) && "Cannot predicate a VSETLN");
// Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
DstReg = MI->getOperand(0).getReg();

20
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -135,24 +135,24 @@ public:
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
// Predication support.
bool isPredicated(const MachineInstr *MI) const override;
bool isPredicated(const MachineInstr &MI) const override;
ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
int PIdx = MI->findFirstPredOperandIdx();
return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
int PIdx = MI.findFirstPredOperandIdx();
return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
: ARMCC::AL;
}
bool PredicateInstruction(MachineInstr *MI,
ArrayRef<MachineOperand> Pred) const override;
bool PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const override;
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
ArrayRef<MachineOperand> Pred2) const override;
bool DefinesPredicate(MachineInstr *MI,
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool isPredicable(MachineInstr *MI) const override;
bool isPredicable(MachineInstr &MI) const override;
/// GetInstSize - Returns the size of the specified MachineInstr.
///
@ -327,7 +327,7 @@ private:
const MCInstrDesc &UseMCID,
unsigned UseIdx, unsigned UseAlign) const;
unsigned getPredicationCost(const MachineInstr *MI) const override;
unsigned getPredicationCost(const MachineInstr &MI) const override;
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
@ -447,7 +447,7 @@ static inline bool isPushOpcode(int Opc) {
/// getInstrPredicate - If instruction is predicated, returns its predicate
/// condition, otherwise returns AL. It also returns the condition code
/// register by reference.
ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
unsigned getMatchingCondBranchOpcode(unsigned Opc);

8
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -1463,14 +1463,14 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
// Avoid splitting an IT block.
if (LastIT) {
unsigned PredReg = 0;
ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
if (CC != ARMCC::AL)
MI = LastIT;
}
// We really must not split an IT block.
DEBUG(unsigned PredReg;
assert(!isThumb || getITInstrPredicate(MI, PredReg) == ARMCC::AL));
assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL));
NewMBB = splitBlockBeforeInstr(MI);
}
@ -1916,7 +1916,7 @@ bool ARMConstantIslands::optimizeThumb2Branches() {
NewOpc = 0;
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg);
if (Pred == ARMCC::EQ)
NewOpc = ARM::tCBZ;
else if (Pred == ARMCC::NE)
@ -1934,7 +1934,7 @@ bool ARMConstantIslands::optimizeThumb2Branches() {
--CmpMI;
if (CmpMI->getOpcode() == ARM::tCMPi8) {
unsigned Reg = CmpMI->getOperand(0).getReg();
Pred = getInstrPredicate(CmpMI, PredReg);
Pred = getInstrPredicate(*CmpMI, PredReg);
if (Pred == ARMCC::AL &&
CmpMI->getOperand(1).getImm() == 0 &&
isARMLowRegister(Reg)) {

2
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -651,7 +651,7 @@ void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
MachineInstr &MI = *MBBI;
unsigned Opcode = MI.getOpcode();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
unsigned DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;

18
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -840,7 +840,7 @@ MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) {
unsigned Base = getLoadStoreBaseOp(*First).getReg();
bool BaseKill = LatestMI->killsRegister(Base);
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(First, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
DebugLoc DL = First->getDebugLoc();
MachineInstr *Merged = nullptr;
if (Cand.CanMergeToLSDouble)
@ -1102,7 +1102,7 @@ static int isIncrementOrDecrement(const MachineInstr &MI, unsigned Reg,
unsigned MIPredReg;
if (MI.getOperand(0).getReg() != Reg ||
MI.getOperand(1).getReg() != Reg ||
getInstrPredicate(&MI, MIPredReg) != Pred ||
getInstrPredicate(MI, MIPredReg) != Pred ||
MIPredReg != PredReg)
return 0;
@ -1169,7 +1169,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineInstr *MI) {
unsigned Base = BaseOP.getReg();
bool BaseKill = BaseOP.isKill();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
unsigned Opcode = MI->getOpcode();
DebugLoc DL = MI->getDebugLoc();
@ -1291,7 +1291,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineInstr *MI) {
return false;
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
int Bytes = getLSMultipleTransferSize(MI);
MachineBasicBlock &MBB = *MI->getParent();
MachineBasicBlock::iterator MBBI(MI);
@ -1388,7 +1388,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSDouble(MachineInstr &MI) const {
return false;
unsigned PredReg;
ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
MachineBasicBlock::iterator MBBI(MI);
MachineBasicBlock &MBB = *MI.getParent();
int Offset;
@ -1549,7 +1549,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
int OffImm = getMemoryOpOffset(MI);
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
if (OddRegNum > EvenRegNum && OffImm == 0) {
// Ascending register numbers and no offset. It's safe to change it to a
@ -1655,7 +1655,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
unsigned Reg = MO.getReg();
unsigned Base = getLoadStoreBaseOp(*MBBI).getReg();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
int Offset = getMemoryOpOffset(MBBI);
if (CurrBase == 0) {
// Start of a new chain.
@ -2056,7 +2056,7 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
if (FirstReg == SecondReg)
return false;
BaseReg = Op0->getOperand(1).getReg();
Pred = getInstrPredicate(Op0, PredReg);
Pred = getInstrPredicate(*Op0, PredReg);
dl = Op0->getDebugLoc();
return true;
}
@ -2250,7 +2250,7 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
if (!isMemoryOp(*MI))
continue;
unsigned PredReg = 0;
if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
if (getInstrPredicate(*MI, PredReg) != ARMCC::AL)
continue;
int Opc = MI->getOpcode();

2
llvm/lib/Target/ARM/ARMSchedule.td
View File

@ -94,7 +94,7 @@ def : PredicateProlog<[{
(void)TII;
}]>;
def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(MI)}]>;
def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(*MI)}]>;
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM

6
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
View File

@ -165,7 +165,7 @@ Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
++I;
if (I != E) {
unsigned NPredReg = 0;
ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg);
if (NCC == CC || NCC == OCC)
return true;
}
@ -182,7 +182,7 @@ bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
MachineInstr *MI = &*MBBI;
DebugLoc dl = MI->getDebugLoc();
unsigned PredReg = 0;
ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
if (CC == ARMCC::AL) {
++MBBI;
continue;
@ -222,7 +222,7 @@ bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
MI = NMI;
unsigned NPredReg = 0;
ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg);
ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg);
if (NCC == CC || NCC == OCC) {
Mask |= (NCC & 1) << Pos;
// Add implicit use of ITSTATE.

12
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -58,7 +58,7 @@ Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
// If the first instruction of Tail is predicated, we may have to update
// the IT instruction.
unsigned PredReg = 0;
ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg);
MachineBasicBlock::iterator MBBI = Tail;
if (CC != ARMCC::AL)
// Expecting at least the t2IT instruction before it.
@ -106,7 +106,7 @@ Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
}
unsigned PredReg = 0;
return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL;
}
void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
@ -459,7 +459,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
Offset += MI.getOperand(FrameRegIdx+1).getImm();
unsigned PredReg;
if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL) {
// Turn it into a move.
MI.setDesc(TII.get(ARM::tMOVr));
MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
@ -627,9 +627,9 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
return Offset == 0;
}
ARMCC::CondCodes
llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
unsigned Opc = MI->getOpcode();
ARMCC::CondCodes llvm::getITInstrPredicate(const MachineInstr &MI,
unsigned &PredReg) {
unsigned Opc = MI.getOpcode();
if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
return ARMCC::AL;
return getInstrPredicate(MI, PredReg);

4
llvm/lib/Target/ARM/Thumb2InstrInfo.h
View File

@ -70,9 +70,7 @@ private:
/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
/// to llvm::getInstrPredicate except it returns AL for conditional branch
/// instructions which are "predicated", but are not in IT blocks.
ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
}
#endif

6
llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -597,7 +597,7 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
case ARM::t2ADDSri:
case ARM::t2ADDSrr: {
unsigned PredReg = 0;
if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) {
switch (Opc) {
default: break;
case ARM::t2ADDSri: {
@ -702,7 +702,7 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
// Check if it's possible / necessary to transfer the predicate.
const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
bool SkipPred = false;
if (Pred != ARMCC::AL) {
if (!NewMCID.isPredicable())
@ -798,7 +798,7 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
// Check if it's possible / necessary to transfer the predicate.
const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
bool SkipPred = false;
if (Pred != ARMCC::AL) {
if (!NewMCID.isPredicable())

2
llvm/lib/Target/BPF/BPFInstrInfo.cpp
View File

@ -90,7 +90,7 @@ bool BPFInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// Working from the bottom, when we see a non-terminator
// instruction, we're done.
if (!isUnpredicatedTerminator(I))
if (!isUnpredicatedTerminator(*I))
break;
// A terminator that isn't a branch can't easily be handled

2
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
View File

@ -937,7 +937,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr *BI,
bool HexagonEvaluator::evaluateLoad(const MachineInstr *MI,
const CellMapType &Inputs, CellMapType &Outputs) const {
if (TII.isPredicated(MI))
if (TII.isPredicated(*MI))
return false;
assert(MI->mayLoad() && "A load that mayn't?");
unsigned Opc = MI->getOpcode();

2
llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
View File

@ -445,7 +445,7 @@ unsigned HexagonEarlyIfConversion::computePhiCost(MachineBasicBlock *B) const {
}
MachineInstr *Def1 = MRI->getVRegDef(RO1.getReg());
MachineInstr *Def3 = MRI->getVRegDef(RO3.getReg());
if (!TII->isPredicable(Def1) || !TII->isPredicable(Def3))
if (!TII->isPredicable(*Def1) || !TII->isPredicable(*Def3))
Cost++;
}
return Cost;

26
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
View File

@ -421,7 +421,7 @@ void HexagonExpandCondsets::addInstrToLiveness(MachineInstr *MI) {
DEBUG(dbgs() << "adding liveness info for instr\n " << MX << " " << *MI);
MX = MX.getRegSlot();
bool Predicated = HII->isPredicated(MI);
bool Predicated = HII->isPredicated(*MI);
MachineBasicBlock *MB = MI->getParent();
// Strip all implicit uses from predicated instructions. They will be
@ -748,7 +748,7 @@ bool HexagonExpandCondsets::splitInBlock(MachineBasicBlock &B) {
bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
if (HII->isPredicated(MI) || !HII->isPredicable(MI))
if (HII->isPredicated(*MI) || !HII->isPredicable(*MI))
return false;
if (MI->hasUnmodeledSideEffects() || MI->mayStore())
return false;
@ -784,8 +784,8 @@ MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
MachineInstr *MI = &*I;
// Check if this instruction can be ignored, i.e. if it is predicated
// on the complementary condition.
if (PredValid && HII->isPredicated(MI)) {
if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(MI)))
if (PredValid && HII->isPredicated(*MI)) {
if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
continue;
}
@ -945,9 +945,9 @@ void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
MachineInstr *MI = &*I;
// Do not touch instructions that are not predicated, or are predicated
// on the opposite condition.
if (!HII->isPredicated(MI))
if (!HII->isPredicated(*MI))
continue;
if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI)))
if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI)))
continue;
for (auto &Op : MI->operands()) {
@ -1014,8 +1014,8 @@ bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond) {
// By default assume that the instruction executes on the same condition
// as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
unsigned Exec = Exec_Then | Exec_Else;
if (PredValid && HII->isPredicated(MI) && MI->readsRegister(PredR))
Exec = (Cond == HII->isPredicatedTrue(MI)) ? Exec_Then : Exec_Else;
if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else;
for (auto &Op : MI->operands()) {
if (!Op.isReg())
@ -1119,11 +1119,9 @@ void HexagonExpandCondsets::removeImplicitUses(MachineInstr *MI) {
void HexagonExpandCondsets::removeImplicitUses(MachineBasicBlock &B) {
for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
MachineInstr *MI = &*I;
for (MachineInstr &MI : B)
if (HII->isPredicated(MI))
removeImplicitUses(MI);
}
removeImplicitUses(&MI);
}
@ -1290,13 +1288,13 @@ bool HexagonExpandCondsets::coalesceSegments(MachineFunction &MF) {
if (S1.isReg()) {
RegisterRef RS = S1;
MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
if (!RDef || !HII->isPredicable(RDef))
if (!RDef || !HII->isPredicable(*RDef))
Done = coalesceRegisters(RD, RegisterRef(S1));
}
if (!Done && S2.isReg()) {
RegisterRef RS = S2;
MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
if (!RDef || !HII->isPredicable(RDef))
if (!RDef || !HII->isPredicable(*RDef))
Done = coalesceRegisters(RD, RegisterRef(S2));
}
Changed |= Done;

4
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
View File

@ -1772,8 +1772,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
for (auto &In : B) {
int LFI, SFI;
bool Load = HII.isLoadFromStackSlot(&In, LFI) && !HII.isPredicated(&In);
bool Store = HII.isStoreToStackSlot(&In, SFI) && !HII.isPredicated(&In);
bool Load = HII.isLoadFromStackSlot(&In, LFI) && !HII.isPredicated(In);
bool Store = HII.isStoreToStackSlot(&In, SFI) && !HII.isPredicated(In);
if (Load && Store) {
// If it's both a load and a store, then we won't handle it.
BadFIs.insert(LFI);

117
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -424,7 +424,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
return false;
--I;
}
if (!isUnpredicatedTerminator(&*I))
if (!isUnpredicatedTerminator(*I))
return false;
// Get the last instruction in the block.
@ -432,7 +432,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
MachineInstr *SecondLastInst = nullptr;
// Find one more terminator if present.
for (;;) {
if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(&*I)) {
if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
if (!SecondLastInst)
SecondLastInst = &*I;
else
@ -585,7 +585,7 @@ unsigned HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,
MachineBasicBlock *NewTBB, *NewFBB;
SmallVector<MachineOperand, 4> Cond;
MachineInstr *Term = MBB.getFirstTerminator();
if (Term != MBB.end() && isPredicated(Term) &&
if (Term != MBB.end() && isPredicated(*Term) &&
!AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
MachineBasicBlock *NextBB = &*++MBB.getIterator();
if (NewTBB == NextBB) {
@ -1211,20 +1211,19 @@ void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
// if (!p0.new) R1 = add(R2, R3)
// Note: New-value stores are not included here as in the current
// implementation, we don't need to check their predicate sense.
bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
const uint64_t F = MI->getDesc().TSFlags;
bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
const uint64_t F = MI.getDesc().TSFlags;
return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
}
bool HexagonInstrInfo::PredicateInstruction(MachineInstr *MI,
ArrayRef<MachineOperand> Cond) const {
bool HexagonInstrInfo::PredicateInstruction(
MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
isEndLoopN(Cond[0].getImm())) {
DEBUG(dbgs() << "\nCannot predicate:"; MI->dump(););
DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
return false;
}
int Opc = MI->getOpcode();
int Opc = MI.getOpcode();
assert (isPredicable(MI) && "Expected predicable instruction");
bool invertJump = predOpcodeHasNot(Cond);
@ -1233,13 +1232,13 @@ bool HexagonInstrInfo::PredicateInstruction(MachineInstr *MI,
// plicated manipulations with the operands (handling tied operands,
// etc.), build a new temporary instruction, then overwrite MI with it.
MachineBasicBlock &B = *MI->getParent();
DebugLoc DL = MI->getDebugLoc();
MachineBasicBlock &B = *MI.getParent();
DebugLoc DL = MI.getDebugLoc();
unsigned PredOpc = getCondOpcode(Opc, invertJump);
MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
unsigned NOp = 0, NumOps = MI->getNumOperands();
unsigned NOp = 0, NumOps = MI.getNumOperands();
while (NOp < NumOps) {
MachineOperand &Op = MI->getOperand(NOp);
MachineOperand &Op = MI.getOperand(NOp);
if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
break;
T.addOperand(Op);
@ -1252,13 +1251,13 @@ bool HexagonInstrInfo::PredicateInstruction(MachineInstr *MI,
assert(GotPredReg);
T.addReg(PredReg, PredRegFlags);
while (NOp < NumOps)
T.addOperand(MI->getOperand(NOp++));
T.addOperand(MI.getOperand(NOp++));
MI->setDesc(get(PredOpc));
while (unsigned n = MI->getNumOperands())
MI->RemoveOperand(n-1);
MI.setDesc(get(PredOpc));
while (unsigned n = MI.getNumOperands())
MI.RemoveOperand(n-1);
for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
MI->addOperand(T->getOperand(i));
MI.addOperand(T->getOperand(i));
MachineBasicBlock::instr_iterator TI = T->getIterator();
B.erase(TI);
@ -1275,12 +1274,11 @@ bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
return false;
}
bool HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
bool HexagonInstrInfo::DefinesPredicate(
MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
auto &HRI = getRegisterInfo();
for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
MachineOperand MO = MI->getOperand(oper);
for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
MachineOperand MO = MI.getOperand(oper);
if (MO.isReg() && MO.isDef()) {
const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
if (RC == &Hexagon::PredRegsRegClass) {
@ -1292,14 +1290,14 @@ bool HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
return false;
}
bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
bool isPred = MI->getDesc().isPredicable();
bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
bool isPred = MI.getDesc().isPredicable();
if (!isPred)
return false;
const int Opc = MI->getOpcode();
int NumOperands = MI->getNumOperands();
const int Opc = MI.getOpcode();
int NumOperands = MI.getNumOperands();
// Keep a flag for upto 4 operands in the instructions, to indicate if
// that operand has been constant extended.
@ -1308,64 +1306,64 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
NumOperands = 4;
for (int i = 0; i < NumOperands; i++)
OpCExtended[i] = (isOperandExtended(MI, i) && isConstExtended(MI));
OpCExtended[i] = (isOperandExtended(&MI, i) && isConstExtended(&MI));
switch(Opc) {
case Hexagon::A2_tfrsi:
return (isOperandExtended(MI, 1) && isConstExtended(MI)) ||
isInt<12>(MI->getOperand(1).getImm());
return (isOperandExtended(&MI, 1) && isConstExtended(&MI)) ||
isInt<12>(MI.getOperand(1).getImm());
case Hexagon::S2_storerd_io:
return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
return isShiftedUInt<6,3>(MI.getOperand(1).getImm());
case Hexagon::S2_storeri_io:
case Hexagon::S2_storerinew_io:
return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
return isShiftedUInt<6,2>(MI.getOperand(1).getImm());
case Hexagon::S2_storerh_io:
case Hexagon::S2_storerhnew_io:
return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
return isShiftedUInt<6,1>(MI.getOperand(1).getImm());
case Hexagon::S2_storerb_io:
case Hexagon::S2_storerbnew_io:
return isUInt<6>(MI->getOperand(1).getImm());
return isUInt<6>(MI.getOperand(1).getImm());
case Hexagon::L2_loadrd_io:
return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
return isShiftedUInt<6,3>(MI.getOperand(2).getImm());
case Hexagon::L2_loadri_io:
return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
return isShiftedUInt<6,2>(MI.getOperand(2).getImm());
case Hexagon::L2_loadrh_io:
case Hexagon::L2_loadruh_io:
return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
return isShiftedUInt<6,1>(MI.getOperand(2).getImm());
case Hexagon::L2_loadrb_io:
case Hexagon::L2_loadrub_io:
return isUInt<6>(MI->getOperand(2).getImm());
return isUInt<6>(MI.getOperand(2).getImm());
case Hexagon::L2_loadrd_pi:
return isShiftedInt<4,3>(MI->getOperand(3).getImm());
return isShiftedInt<4,3>(MI.getOperand(3).getImm());
case Hexagon::L2_loadri_pi:
return isShiftedInt<4,2>(MI->getOperand(3).getImm());
return isShiftedInt<4,2>(MI.getOperand(3).getImm());
case Hexagon::L2_loadrh_pi:
case Hexagon::L2_loadruh_pi:
return isShiftedInt<4,1>(MI->getOperand(3).getImm());
return isShiftedInt<4,1>(MI.getOperand(3).getImm());
case Hexagon::L2_loadrb_pi:
case Hexagon::L2_loadrub_pi:
return isInt<4>(MI->getOperand(3).getImm());
return isInt<4>(MI.getOperand(3).getImm());
case Hexagon::S4_storeirb_io:
case Hexagon::S4_storeirh_io:
case Hexagon::S4_storeiri_io:
return (OpCExtended[1] || isUInt<6>(MI->getOperand(1).getImm())) &&
(OpCExtended[2] || isInt<6>(MI->getOperand(2).getImm()));
return (OpCExtended[1] || isUInt<6>(MI.getOperand(1).getImm())) &&
(OpCExtended[2] || isInt<6>(MI.getOperand(2).getImm()));
case Hexagon::A2_addi:
return isInt<8>(MI->getOperand(2).getImm());
return isInt<8>(MI.getOperand(2).getImm());
case Hexagon::A2_aslh:
case Hexagon::A2_asrh:
@ -1662,13 +1660,13 @@ bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr *MI) const {
bool HexagonInstrInfo::isCondInst(const MachineInstr *MI) const {
return (MI->isBranch() && isPredicated(MI)) ||
return (MI->isBranch() && isPredicated(*MI)) ||
isConditionalTransfer(MI) ||
isConditionalALU32(MI) ||
isConditionalLoad(MI) ||
// Predicated stores which don't have a .new on any operands.
(MI->mayStore() && isPredicated(MI) && !isNewValueStore(MI) &&
!isPredicatedNew(MI));
(MI->mayStore() && isPredicated(*MI) && !isNewValueStore(MI) &&
!isPredicatedNew(*MI));
}
@ -1733,7 +1731,7 @@ bool HexagonInstrInfo::isConditionalALU32(const MachineInstr* MI) const {
// FIXME - Function name and it's functionality don't match.
// It should be renamed to hasPredNewOpcode()
bool HexagonInstrInfo::isConditionalLoad(const MachineInstr* MI) const {
if (!MI->getDesc().mayLoad() || !isPredicated(MI))
if (!MI->getDesc().mayLoad() || !isPredicated(*MI))
return false;
int PNewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
@ -1939,8 +1937,7 @@ bool HexagonInstrInfo::isDotCurInst(const MachineInstr* MI) const {
// Returns true, if any one of the operands is a dot new
// insn, whether it is predicated dot new or register dot new.
bool HexagonInstrInfo::isDotNewInst(const MachineInstr* MI) const {
if (isNewValueInst(MI) ||
(isPredicated(MI) && isPredicatedNew(MI)))
if (isNewValueInst(MI) || (isPredicated(*MI) && isPredicatedNew(*MI)))
return true;
return false;
@ -2305,8 +2302,8 @@ bool HexagonInstrInfo::isPostIncrement(const MachineInstr* MI) const {
}
bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
const uint64_t F = MI->getDesc().TSFlags;
bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
const uint64_t F = MI.getDesc().TSFlags;
assert(isPredicated(MI));
return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
}
@ -2319,8 +2316,8 @@ bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
}
bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const {
const uint64_t F = MI->getDesc().TSFlags;
bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
const uint64_t F = MI.getDesc().TSFlags;
return !((F >> HexagonII::PredicatedFalsePos) &
HexagonII::PredicatedFalseMask);
}
@ -3084,7 +3081,7 @@ bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
} else
return false;
if (isPredicated(MI)) {
if (isPredicated(*MI)) {
BasePos++;
OffsetPos++;
}
@ -3138,7 +3135,7 @@ SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
return Jumpers;
--I;
}
if (!isUnpredicatedTerminator(&*I))
if (!isUnpredicatedTerminator(*I))
return Jumpers;
// Get the last instruction in the block.
@ -3147,7 +3144,7 @@ SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
MachineInstr *SecondLastInst = nullptr;
// Find one more terminator if present.
do {
if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(&*I)) {
if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
if (!SecondLastInst) {
SecondLastInst = &*I;
Jumpers.push_back(SecondLastInst);
@ -4106,7 +4103,7 @@ bool HexagonInstrInfo::invertAndChangeJumpTarget(
--TargetPos;
assert((TargetPos >= 0) && MI->getOperand(TargetPos).isMBB());
MI->getOperand(TargetPos).setMBB(NewTarget);
if (EnableBranchPrediction && isPredicatedNew(MI)) {
if (EnableBranchPrediction && isPredicatedNew(*MI)) {
NewOpcode = reversePrediction(NewOpcode);
}
MI->setDesc(get(NewOpcode));

12
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
View File

@ -183,11 +183,11 @@ public:
MachineBasicBlock::iterator MI) const override;
/// Returns true if the instruction is already predicated.
bool isPredicated(const MachineInstr *MI) const override;
bool isPredicated(const MachineInstr &MI) const override;
/// Convert the instruction into a predicated instruction.
/// It returns true if the operation was successful.
bool PredicateInstruction(MachineInstr *MI,
bool PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Cond) const override;
/// Returns true if the first specified predicate
@ -198,13 +198,13 @@ public:
/// If the specified instruction defines any predicate
/// or condition code register(s) used for predication, returns true as well
/// as the definition predicate(s) by reference.
bool DefinesPredicate(MachineInstr *MI,
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
/// Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a
/// PredicateOperand.
bool isPredicable(MachineInstr *MI) const override;
bool isPredicable(MachineInstr &MI) const override;
/// Test if the given instruction should be considered a scheduling boundary.
/// This primarily includes labels and terminators.
@ -301,9 +301,9 @@ public:
bool isNewValueStore(unsigned Opcode) const;
bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
bool isPostIncrement(const MachineInstr* MI) const;
bool isPredicatedNew(const MachineInstr *MI) const;
bool isPredicatedNew(const MachineInstr &MI) const;
bool isPredicatedNew(unsigned Opcode) const;
bool isPredicatedTrue(const MachineInstr *MI) const;
bool isPredicatedTrue(const MachineInstr &MI) const;
bool isPredicatedTrue(unsigned Opcode) const;
bool isPredicated(unsigned Opcode) const;
bool isPredicateLate(unsigned Opcode) const;

2
llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
View File

@ -116,7 +116,7 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
MachineFunction &MF) {
// Predicated instruction can not be feeder to NVJ.
if (QII->isPredicated(II))
if (QII->isPredicated(*II))
return false;
// Bail out if feederReg is a paired register (double regs in

2
llvm/lib/Target/Hexagon/HexagonPeephole.cpp
View File

@ -243,7 +243,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
// Look for Predicated instructions.
if (!DisablePNotP) {
bool Done = false;
if (QII->isPredicated(MI)) {
if (QII->isPredicated(*MI)) {
MachineOperand &Op0 = MI->getOperand(0);
unsigned Reg0 = Op0.getReg();
const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);

32
llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
View File

@ -436,7 +436,7 @@ enum PredicateKind {
/// Returns true if an instruction is predicated on p0 and false if it's
/// predicated on !p0.
static PredicateKind getPredicateSense(const MachineInstr *MI,
static PredicateKind getPredicateSense(const MachineInstr &MI,
const HexagonInstrInfo *HII) {
if (!HII->isPredicated(MI))
return PK_Unknown;
@ -570,8 +570,8 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr *MI,
// If the source that feeds the store is predicated, new value store must
// also be predicated.
if (HII->isPredicated(PacketMI)) {
if (!HII->isPredicated(MI))
if (HII->isPredicated(*PacketMI)) {
if (!HII->isPredicated(*MI))
return false;
// Check to make sure that they both will have their predicates
@ -613,8 +613,8 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr *MI,
// 3) Both new-value register producer and user should have same predicate
// sense, i.e, either both should be negated or both should be non-negated.
if (predRegNumDst != predRegNumSrc ||
HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
getPredicateSense(MI, HII) != getPredicateSense(PacketMI, HII))
HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
getPredicateSense(*MI, HII) != getPredicateSense(*PacketMI, HII))
return false;
}
@ -793,7 +793,7 @@ bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr* MI,
for (auto I : CurrentPacketMIs) {
// We only care for dependencies to predicated instructions
if (!HII->isPredicated(I))
if (!HII->isPredicated(*I))
continue;
// Scheduling Unit for current insn in the packet
@ -817,13 +817,13 @@ bool HexagonPacketizerList::restrictingDepExistInPacket(MachineInstr* MI,
/// Gets the predicate register of a predicated instruction.
static unsigned getPredicatedRegister(MachineInstr *MI,
static unsigned getPredicatedRegister(MachineInstr &MI,
const HexagonInstrInfo *QII) {
/// We use the following rule: The first predicate register that is a use is
/// the predicate register of a predicated instruction.
assert(QII->isPredicated(MI) && "Must be predicated instruction");
for (auto &Op : MI->operands()) {
for (auto &Op : MI.operands()) {
if (Op.isReg() && Op.getReg() && Op.isUse() &&
Hexagon::PredRegsRegClass.contains(Op.getReg()))
return Op.getReg();
@ -835,8 +835,8 @@ static unsigned getPredicatedRegister(MachineInstr *MI,
// Given two predicated instructions, this function detects whether
// the predicates are complements.
bool HexagonPacketizerList::arePredicatesComplements(MachineInstr *MI1,
MachineInstr *MI2) {
bool HexagonPacketizerList::arePredicatesComplements(MachineInstr &MI1,
MachineInstr &MI2) {
// If we don't know the predicate sense of the instructions bail out early, we
// need it later.
if (getPredicateSense(MI1, HII) == PK_Unknown ||
@ -844,7 +844,7 @@ bool HexagonPacketizerList::arePredicatesComplements(MachineInstr *MI1,
return false;
// Scheduling unit for candidate.
SUnit *SU = MIToSUnit[MI1];
SUnit *SU = MIToSUnit[&MI1];
// One corner case deals with the following scenario:
// Trying to add
@ -898,7 +898,7 @@ bool HexagonPacketizerList::arePredicatesComplements(MachineInstr *MI1,
Hexagon::PredRegsRegClass.contains(PReg1) &&
Hexagon::PredRegsRegClass.contains(PReg2) &&
getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
HII->isDotNewInst(MI1) == HII->isDotNewInst(MI2);
HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2);
}
// Initialize packetizer flags.
@ -1045,7 +1045,7 @@ bool HexagonPacketizerList::hasDeadDependence(const MachineInstr *I,
// defining the same (dead) register.
if (I->isCall() || J->isCall())
return false;
if (HII->isPredicated(I) || HII->isPredicated(J))
if (HII->isPredicated(*I) || HII->isPredicated(*J))
return false;
BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);
@ -1085,7 +1085,7 @@ bool HexagonPacketizerList::hasControlDependence(const MachineInstr *I,
auto isBadForLoopN = [this] (const MachineInstr *MI) -> bool {
if (MI->isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
return true;
if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI))
if (HII->isPredicated(*MI) && HII->isPredicatedNew(*MI) && HII->isJumpR(MI))
return true;
return false;
};
@ -1275,8 +1275,8 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
// For predicated instructions, if the predicates are complements then
// there can be no dependence.
if (HII->isPredicated(I) && HII->isPredicated(J) &&
arePredicatesComplements(I, J)) {
if (HII->isPredicated(*I) && HII->isPredicated(*J) &&
arePredicatesComplements(*I, *J)) {
// Not always safe to do this translation.
// DAG Builder attempts to reduce dependence edges using transitive
// nature of dependencies. Here is an example:

2
llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h
View File

@ -93,7 +93,7 @@ protected:
bool canPromoteToNewValueStore(const MachineInstr* MI,
const MachineInstr* PacketMI, unsigned DepReg);
bool demoteToDotOld(MachineInstr* MI);
bool arePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2);
bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
bool restrictingDepExistInPacket(MachineInstr*, unsigned);
bool isNewifiable(const MachineInstr *MI);
bool isCurifiable(MachineInstr* MI);

4
llvm/lib/Target/Hexagon/RDFGraph.cpp
View File

@ -674,7 +674,7 @@ bool RegisterAliasInfo::alias(RegisterRef RA, RegisterRef RB) const {
// unchanged across this def.
bool TargetOperandInfo::isPreserving(const MachineInstr &In, unsigned OpNum)
const {
return TII.isPredicated(&In);
return TII.isPredicated(In);
}
// Check if the definition of RR produces an unspecified value.
@ -1179,7 +1179,7 @@ void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) {
ImpUses.insert({R, 0});
bool IsCall = In.isCall(), IsReturn = In.isReturn();
bool IsPredicated = TII.isPredicated(&In);
bool IsPredicated = TII.isPredicated(In);
unsigned NumOps = In.getNumOperands();
// Avoid duplicate implicit defs. This will not detect cases of implicit

11
llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -156,13 +156,14 @@ ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
return false;
}
bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
if (!MI->isTerminator()) return false;
bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
if (!MI.isTerminator())
return false;
// Conditional branch is a special case.
if (MI->isBranch() && !MI->isBarrier())
if (MI.isBranch() && !MI.isBarrier())
return true;
if (!MI->isPredicable())
if (!MI.isPredicable())
return true;
return !isPredicated(MI);
}
@ -182,7 +183,7 @@ bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// Working from the bottom, when we see a non-terminator
// instruction, we're done.
if (!isUnpredicatedTerminator(I))
if (!isUnpredicatedTerminator(*I))
break;
// A terminator that isn't a branch can't easily be handled

2
llvm/lib/Target/MSP430/MSP430InstrInfo.h
View File

@ -74,7 +74,7 @@ public:
// Branch folding goodness
bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
bool AnalyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,

6
llvm/lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -184,7 +184,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch(
while (I != REnd && I->isDebugValue())
++I;
if (I == REnd || !isUnpredicatedTerminator(&*I)) {
if (I == REnd || !isUnpredicatedTerminator(*I)) {
// This block ends with no branches (it just falls through to its succ).
// Leave TBB/FBB null.
TBB = FBB = nullptr;
@ -208,7 +208,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch(
SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
// Not an analyzable branch (must be an indirect jump).
if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
return BT_None;
}
@ -227,7 +227,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch(
// If we reached here, there are two branches.
// If there are three terminators, we don't know what sort of block this is.
if (++I != REnd && isUnpredicatedTerminator(&*I))
if (++I != REnd && isUnpredicatedTerminator(*I))
return BT_None;
BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);

6
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
View File

@ -150,14 +150,14 @@ bool NVPTXInstrInfo::AnalyzeBranch(
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
// If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
if (I == MBB.begin() || !isUnpredicatedTerminator(*--I))
return false;
// Get the last instruction in the block.
MachineInstr *LastInst = I;
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
if (LastInst->getOpcode() == NVPTX::GOTO) {
TBB = LastInst->getOperand(0).getMBB();
return false;
@ -175,7 +175,7 @@ bool NVPTXInstrInfo::AnalyzeBranch(
MachineInstr *SecondLastInst = I;
// If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
return true;
// If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.

123
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -453,14 +453,14 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
if (I == MBB.end())
return false;
if (!isUnpredicatedTerminator(I))
if (!isUnpredicatedTerminator(*I))
return false;
// Get the last instruction in the block.
MachineInstr *LastInst = I;
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
if (LastInst->getOpcode() == PPC::B) {
if (!LastInst->getOperand(0).isMBB())
return true;
@ -522,8 +522,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineInstr *SecondLastInst = I;
// If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() &&
isUnpredicatedTerminator(--I))
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
return true;
// If the block ends with PPC::B and PPC:BCC, handle it.
@ -1299,7 +1298,7 @@ bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
}
bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
// The predicated branches are identified by their type, not really by the
// explicit presence of a predicate. Furthermore, some of them can be
// predicated more than once. Because if conversion won't try to predicate
@ -1310,73 +1309,71 @@ bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
return false;
}
bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
if (!MI->isTerminator())
bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
if (!MI.isTerminator())
return false;
// Conditional branch is a special case.
if (MI->isBranch() && !MI->isBarrier())
if (MI.isBranch() && !MI.isBarrier())
return true;
return !isPredicated(MI);
}
bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const {
unsigned OpC = MI->getOpcode();
unsigned OpC = MI.getOpcode();
if (OpC == PPC::BLR || OpC == PPC::BLR8) {
if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
bool isPPC64 = Subtarget.isPPC64();
MI->setDesc(get(Pred[0].getImm() ?
(isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
(isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
: (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
} else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
MI->setDesc(get(PPC::BCLR));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addReg(Pred[1].getReg());
MI.setDesc(get(PPC::BCLR));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addReg(Pred[1].getReg());
} else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
MI->setDesc(get(PPC::BCLRn));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addReg(Pred[1].getReg());
MI.setDesc(get(PPC::BCLRn));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addReg(Pred[1].getReg());
} else {
MI->setDesc(get(PPC::BCCLR));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addImm(Pred[0].getImm())
.addReg(Pred[1].getReg());
MI.setDesc(get(PPC::BCCLR));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(Pred[0].getImm())
.addReg(Pred[1].getReg());
}
return true;
} else if (OpC == PPC::B) {
if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
bool isPPC64 = Subtarget.isPPC64();
MI->setDesc(get(Pred[0].getImm() ?
(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
(isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
: (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
} else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
MI->RemoveOperand(0);
MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
MI.RemoveOperand(0);
MI->setDesc(get(PPC::BC));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addReg(Pred[1].getReg())
.addMBB(MBB);
MI.setDesc(get(PPC::BC));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addReg(Pred[1].getReg())
.addMBB(MBB);
} else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
MI->RemoveOperand(0);
MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
MI.RemoveOperand(0);
MI->setDesc(get(PPC::BCn));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addReg(Pred[1].getReg())
.addMBB(MBB);
MI.setDesc(get(PPC::BCn));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addReg(Pred[1].getReg())
.addMBB(MBB);
} else {
MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
MI->RemoveOperand(0);
MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
MI.RemoveOperand(0);
MI->setDesc(get(PPC::BCC));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addImm(Pred[0].getImm())
.addReg(Pred[1].getReg())
.addMBB(MBB);
MI.setDesc(get(PPC::BCC));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(Pred[0].getImm())
.addReg(Pred[1].getReg())
.addMBB(MBB);
}
return true;
@ -1389,24 +1386,24 @@ bool PPCInstrInfo::PredicateInstruction(MachineInstr *MI,
bool isPPC64 = Subtarget.isPPC64();
if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) :
(setLR ? PPC::BCCTRL : PPC::BCCTR)));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addReg(Pred[1].getReg());
MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
: (setLR ? PPC::BCCTRL : PPC::BCCTR)));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addReg(Pred[1].getReg());
return true;
} else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) :
(setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addReg(Pred[1].getReg());
MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
: (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addReg(Pred[1].getReg());
return true;
}
MI->setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) :
(setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addImm(Pred[0].getImm())
.addReg(Pred[1].getReg());
MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
: (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(Pred[0].getImm())
.addReg(Pred[1].getReg());
return true;
}
@ -1444,7 +1441,7 @@ bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
return false;
}
bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const {
// Note: At the present time, the contents of Pred from this function is
// unused by IfConversion. This implementation follows ARM by pushing the
@ -1457,8 +1454,8 @@ bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
&PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
const TargetRegisterClass *RC = RCs[c];
if (MO.isReg()) {
@ -1480,8 +1477,8 @@ bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
return Found;
}
bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
unsigned OpC = MI->getOpcode();
bool PPCInstrInfo::isPredicable(MachineInstr &MI) const {
unsigned OpC = MI.getOpcode();
switch (OpC) {
default:
return false;

10
llvm/lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -230,20 +230,20 @@ public:
}
// Predication support.
bool isPredicated(const MachineInstr *MI) const override;
bool isPredicated(const MachineInstr &MI) const override;
bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
bool PredicateInstruction(MachineInstr *MI,
bool PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const override;
bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
ArrayRef<MachineOperand> Pred2) const override;
bool DefinesPredicate(MachineInstr *MI,
bool DefinesPredicate(MachineInstr &MI,
std::vector<MachineOperand> &Pred) const override;
bool isPredicable(MachineInstr *MI) const override;
bool isPredicable(MachineInstr &MI) const override;
// Comparison optimization.

8
llvm/lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -148,7 +148,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
if (I == MBB.end())
return false;
if (!isUnpredicatedTerminator(I))
if (!isUnpredicatedTerminator(*I))
return false;
// Get the last instruction in the block.
@ -156,7 +156,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
unsigned LastOpc = LastInst->getOpcode();
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
if (isUncondBranchOpcode(LastOpc)) {
TBB = LastInst->getOperand(0).getMBB();
return false;
@ -180,7 +180,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
LastInst->eraseFromParent();
LastInst = SecondLastInst;
LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
// Return now the only terminator is an unconditional branch.
TBB = LastInst->getOperand(0).getMBB();
return false;
@ -192,7 +192,7 @@ bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
}
// If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
return true;
// If the block ends with a B and a Bcc, handle it.

21
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -261,7 +261,7 @@ bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
// Working from the bottom, when we see a non-terminator instruction, we're
// done.
if (!isUnpredicatedTerminator(I))
if (!isUnpredicatedTerminator(*I))
break;
// A terminator that isn't a branch can't easily be handled by this
@ -506,8 +506,8 @@ static unsigned getConditionalMove(unsigned Opcode) {
}
}
bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
unsigned Opcode = MI->getOpcode();
bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
unsigned Opcode = MI.getOpcode();
return STI.hasLoadStoreOnCond() && getConditionalMove(Opcode);
}
@ -529,19 +529,20 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB,
return false;
}
bool SystemZInstrInfo::
PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
bool SystemZInstrInfo::PredicateInstruction(
MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
assert(Pred.size() == 2 && "Invalid condition");
unsigned CCValid = Pred[0].getImm();
unsigned CCMask = Pred[1].getImm();
assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
unsigned Opcode = MI->getOpcode();
unsigned Opcode = MI.getOpcode();
if (STI.hasLoadStoreOnCond()) {
if (unsigned CondOpcode = getConditionalMove(Opcode)) {
MI->setDesc(get(CondOpcode));
MachineInstrBuilder(*MI->getParent()->getParent(), MI)
.addImm(CCValid).addImm(CCMask)
.addReg(SystemZ::CC, RegState::Implicit);
MI.setDesc(get(CondOpcode));
MachineInstrBuilder(*MI.getParent()->getParent(), MI)
.addImm(CCValid)
.addImm(CCMask)
.addReg(SystemZ::CC, RegState::Implicit);
return true;
}
}

4
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
View File

@ -156,7 +156,7 @@ public:
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
unsigned SrcReg2, int Mask, int Value,
const MachineRegisterInfo *MRI) const override;
bool isPredicable(MachineInstr *MI) const override;
bool isPredicable(MachineInstr &MI) const override;
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles,
BranchProbability Probability) const override;
@ -165,7 +165,7 @@ public:
MachineBasicBlock &FMBB,
unsigned NumCyclesF, unsigned ExtraPredCyclesF,
BranchProbability Probability) const override;
bool PredicateInstruction(MachineInstr *MI,
bool PredicateInstruction(MachineInstr &MI,
ArrayRef<MachineOperand> Pred) const override;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
DebugLoc DL, unsigned DestReg, unsigned SrcReg,

10
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -3903,13 +3903,13 @@ unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
}
}
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
if (!MI->isTerminator()) return false;
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
if (!MI.isTerminator()) return false;
// Conditional branch is a special case.
if (MI->isBranch() && !MI->isBarrier())
if (MI.isBranch() && !MI.isBarrier())
return true;
if (!MI->isPredicable())
if (!MI.isPredicable())
return true;
return !isPredicated(MI);
}
@ -3930,7 +3930,7 @@ bool X86InstrInfo::AnalyzeBranchImpl(
// Working from the bottom, when we see a non-terminator instruction, we're
// done.
if (!isUnpredicatedTerminator(I))
if (!isUnpredicatedTerminator(*I))
break;
// A terminator that isn't a branch can't easily be handled by this

2
llvm/lib/Target/X86/X86InstrInfo.h
View File

@ -305,7 +305,7 @@ public:
unsigned SrcOpIdx2) const;
// Branch analysis.
bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,

7
llvm/lib/Target/XCore/XCoreInstrInfo.cpp
View File

@ -200,14 +200,14 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
if (I == MBB.end())
return false;
if (!isUnpredicatedTerminator(I))
if (!isUnpredicatedTerminator(*I))
return false;
// Get the last instruction in the block.
MachineInstr *LastInst = I;
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
if (IsBRU(LastInst->getOpcode())) {
TBB = LastInst->getOperand(0).getMBB();
return false;
@ -230,8 +230,7 @@ XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineInstr *SecondLastInst = I;
// If there are three terminators, we don't know what sort of block this is.
if (SecondLastInst && I != MBB.begin() &&
isUnpredicatedTerminator(--I))
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
return true;
unsigned SecondLastOpc = SecondLastInst->getOpcode();