From 6262bbf819a0bc04871835011d71eb48dc7f0784 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 13 Dec 2012 01:41:15 +0000 Subject: [PATCH] [mips] Modify definitions of floating point conditional move instructions. No functionality change. llvm-svn: 170080 --- llvm/lib/Target/Mips/MipsCondMov.td | 87 +++++++++++++++++------- llvm/lib/Target/Mips/MipsInstrFormats.td | 47 +++++++++++++ 2 files changed, 110 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsCondMov.td b/llvm/lib/Target/Mips/MipsCondMov.td index 457d238a01a5..b78c2bbf668a 100644 --- a/llvm/lib/Target/Mips/MipsCondMov.td +++ b/llvm/lib/Target/Mips/MipsCondMov.td @@ -56,6 +56,31 @@ class CondMovFPFP fmt, bits<1> tf, let Constraints = "$F = $fd"; } +class CMov_I_F_FT : + InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F), + !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> { + let Constraints = "$F = $fd"; +} + +class CMov_F_I_FT : + InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F), + !strconcat(opstr, "\t$rd, $rs, $$fcc0"), + [(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> { + let Uses = [FCR31]; + let Constraints = "$F = $rd"; +} + +class CMov_F_F_FT : + InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F), + !strconcat(opstr, "\t$fd, $fs, $$fcc0"), + [(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> { + let Uses = [FCR31]; + let Constraints = "$F = $fd"; +} + // select patterns multiclass MovzPats0; -def MOVZ_I64_S : CondMovIntFP, - Requires<[HasMips64, HasStdEnc]> { +def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegs, FGR32, IIFmove>, + CMov_I_F_FM<18, 16>; +def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64Regs, FGR32, IIFmove>, + CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> { let DecoderNamespace = "Mips64"; } -def MOVN_I_S : CondMovIntFP; -def MOVN_I64_S : CondMovIntFP, - Requires<[HasMips64, HasStdEnc]> { +def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegs, FGR32, IIFmove>, + CMov_I_F_FM<19, 16>; +def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64Regs, FGR32, IIFmove>, + CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> { let DecoderNamespace = "Mips64"; } let Predicates = [NotFP64bit, HasStdEnc] in { - def MOVZ_I_D32 : CondMovIntFP; - def MOVN_I_D32 : CondMovIntFP; + def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegs, AFGR64, IIFmove>, + CMov_I_F_FM<18, 17>; + def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegs, AFGR64, IIFmove>, + CMov_I_F_FM<19, 17>; } let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { - def MOVZ_I_D64 : CondMovIntFP; - def MOVZ_I64_D64 : CondMovIntFP { + def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegs, FGR64, IIFmove>, + CMov_I_F_FM<18, 17>; + def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64Regs, FGR64, IIFmove>, + CMov_I_F_FM<18, 17> { let isCodeGenOnly = 1; } - def MOVN_I_D64 : CondMovIntFP; - def MOVN_I64_D64 : CondMovIntFP { + def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegs, FGR64, IIFmove>, + CMov_I_F_FM<19, 17>; + def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64Regs, FGR64, IIFmove>, + CMov_I_F_FM<19, 17> { let isCodeGenOnly = 1; } } -def MOVT_I : CondMovFPInt; -def MOVT_I64 : CondMovFPInt, - Requires<[HasMips64, HasStdEnc]> { +def MOVT_I : CMov_F_I_FT<"movt", CPURegs, IIAlu, MipsCMovFP_T>, CMov_F_I_FM<1>; +def MOVT_I64 : CMov_F_I_FT<"movt", CPU64Regs, IIAlu, MipsCMovFP_T>, + CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> { let DecoderNamespace = "Mips64"; } -def MOVF_I : CondMovFPInt; -def MOVF_I64 : CondMovFPInt, - Requires<[HasMips64, HasStdEnc]> { +def MOVF_I : CMov_F_I_FT<"movf", CPURegs, IIAlu, MipsCMovFP_F>, CMov_F_I_FM<0>; +def MOVF_I64 : CMov_F_I_FT<"movf", CPU64Regs, IIAlu, MipsCMovFP_F>, + CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> { let DecoderNamespace = "Mips64"; } -def MOVT_S : CondMovFPFP; -def MOVF_S : CondMovFPFP; +def MOVT_S : CMov_F_F_FT<"movt.s", FGR32, IIFmove, MipsCMovFP_T>, + CMov_F_F_FM<16, 1>; +def MOVF_S : CMov_F_F_FT<"movf.s", FGR32, IIFmove, MipsCMovFP_F>, + CMov_F_F_FM<16, 0>; let Predicates = [NotFP64bit, HasStdEnc] in { - def MOVT_D32 : CondMovFPFP; - def MOVF_D32 : CondMovFPFP; + def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64, IIFmove, MipsCMovFP_T>, + CMov_F_F_FM<17, 1>; + def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64, IIFmove, MipsCMovFP_F>, + CMov_F_F_FM<17, 0>; } let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { - def MOVT_D64 : CondMovFPFP; - def MOVF_D64 : CondMovFPFP; + def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64, IIFmove, MipsCMovFP_T>, + CMov_F_F_FM<17, 1>; + def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64, IIFmove, MipsCMovFP_F>, + CMov_F_F_FM<17, 0>; } // Instantiation of conditional move patterns. diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td index 97fdab9e1840..e4d0a2067f75 100644 --- a/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -482,3 +482,50 @@ class CEQS_FM fmt> { let Inst{7-4} = 0x3; let Inst{3-0} = cond; } + +class CMov_I_F_FM funct, bits<5> fmt> { + bits<5> fd; + bits<5> fs; + bits<5> rt; + + bits<32> Inst; + + let Inst{31-26} = 0x11; + let Inst{25-21} = fmt; + let Inst{20-16} = rt; + let Inst{15-11} = fs; + let Inst{10-6} = fd; + let Inst{5-0} = funct; +} + +class CMov_F_I_FM { + bits<5> rd; + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = 0; + let Inst{25-21} = rs; + let Inst{20-18} = 0; // cc + let Inst{17} = 0; + let Inst{16} = tf; + let Inst{15-11} = rd; + let Inst{10-6} = 0; + let Inst{5-0} = 1; +} + +class CMov_F_F_FM fmt, bit tf> { + bits<5> fd; + bits<5> fs; + + bits<32> Inst; + + let Inst{31-26} = 0x11; + let Inst{25-21} = fmt; + let Inst{20-18} = 0; // cc + let Inst{17} = 0; + let Inst{16} = tf; + let Inst{15-11} = fs; + let Inst{10-6} = fd; + let Inst{5-0} = 0x11; +}