replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

ARM assembly aliases for BIC<-->AND (immediate). 

When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.

rdar://10550057

llvm-svn: 146283
This commit is contained in:
Jim Grosbach 2011-12-09 22:02:17 +00:00
parent 1d54d2210a
commit 6192b6570d
3 changed files with 29 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -5050,6 +5050,20 @@ def : MnemonicAlias<"usubaddx", "usax">;
// for isel.
def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
(MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
// Same for AND <--> BIC
def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
(ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
(ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
(BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
(BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
pred:$p, cc_out:$s)>;
// Likewise, "add Rd, so_imm_neg" -> sub
def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
(SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;

13
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -4097,6 +4097,19 @@ def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
// for isel.
def : t2InstAlias<"mov${p} $Rd, $imm",
(t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
// Same for AND <--> BIC
def : t2InstAlias<"bic${s}${p} $Rd, $Rn, $imm",
(t2ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : t2InstAlias<"bic${s}${p} $Rdn, $imm",
(t2ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : t2InstAlias<"and${s}${p} $Rd, $Rn, $imm",
(t2BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
pred:$p, cc_out:$s)>;
def : t2InstAlias<"and${s}${p} $Rdn, $imm",
(t2BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
pred:$p, cc_out:$s)>;
// Likewise, "add Rd, so_imm_neg" -> sub
def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
(t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,

2
llvm/test/MC/ARM/basic-arm-instructions.s
View File

@ -222,6 +222,7 @@ Lforward:
and r6, r7, r8, asr r2
and r6, r7, r8, ror r2
and r10, r1, r6, rrx
and r2, r3, #0x7fffffff
@ destination register is optional
and r1, #0xf
@ -249,6 +250,7 @@ Lforward:
@ CHECK: and r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0x07,0xe0]
@ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0]
@ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0]
@ CHECK: bic r2, r3, #-2147483648 @ encoding: [0x02,0x21,0xc3,0xe3]
@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2]
@ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0]