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Fix a very bad typo. Since the register number was off by one, the ARM 

load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.

llvm-svn: 99043
This commit is contained in:
Bob Wilson 2010-03-20 06:05:13 +00:00
parent 4c43e31d21
commit 614d1fdfc3
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
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@ -80,7 +80,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
case D23: return 23;
case D24: return 24;
case D25: return 25;
case D26: return 27;
case D26: return 26;
case D27: return 27;
case D28: return 28;
case D29: return 29;